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參數(shù)資料
| 型號： | LTC6915IGN#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PGA DIGITAL PREC 0DRFT 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 放大器類型： | 儀表 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 0.2 V/µs |
| 增益帶寬積： | 200kHz |
| 電流 - 輸入偏壓： | 4nA |
| 電壓 - 輸入偏移： | 5µV |
| 電流 - 電源： | 1.73mA |
| 電壓 - 電源，單路/雙路(±)： | 2.7 V ~ 11 V，±1.35 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
LTC6915
6
6915fb
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: These parameters are tested at ±5V supply; at 3V and 5V supplies
they are guaranteed by design.
Note 3: These parameters are guaranteed by design. Thermocouple effects
preclude measurement of these voltage levels in high speed automatic test
systems. VOS is measured to a limit set by test equipment capability.
Note 4: If the total source resistance is less than 10k, no DC errors result
from the input bias current or mismatch of the input bias currents or the
mismatch of the resistances connected to IN– and IN+.
Note 5: The PSRR measurement accuracy depends on the proximity of
the power supply bypass capacitor to the device under test. Because of
this, the PSRR is 100% tested to relaxed limits at final test. However, their
values are guaranteed by design to meet the data sheet limits.
Note 6: Supply current is dependent on the clock frequency. A higher clock
frequency results in higher supply current.
Note 7: Guaranteed by design, not subject to test.
elecTrical characTerisTics The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
Timing, V+ = 4.5V to 5.5V, V– = 0V (Note 7)
t1
DIN Valid to CLK Setup
l
30
ns
t2
DIN Valid to CLK Hold
l
0
ns
t3
CLK Low
l
50
ns
t4
CLK High
l
50
ns
t5
CS/LD Pulse Width
l
40
ns
t6
LSB CLK to CS/LD
l
40
ns
t7
CS/LD Low to CLK
l
20
ns
t8
DOUT Output Delay
CL = 15pF
l
85
ns
t9
CLK Low to CS/LD Low
l
0
ns
Timing, Dual ±4.5V to ±5.5V Supplies (Note 7)
t1
DIN Valid to CLK Setup
l
30
ns
t2
DIN Valid to CLK Hold
l
0
ns
t3
CLK High
l
50
ns
t4
CLK Low
l
50
ns
t5
CS/LD Pulse Width
l
40
ns
t6
LSB CLK to CS/LD
l
40
ns
t7
CS/LD Low to CLK
l
20
ns
t8
DOUT Output Delay
CL = 15pF
l
85
ns
t9
CLK Low to CS/LD Low
l
0
ns
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