參數(shù)資料
型號(hào)： LTC6078
廠商： Linear Technology Corporation
英文描述： 16-/14-/12-Bit VOUT DACs in 3mm 】 3mm DFN
中文描述： 16/14/12 VOUT電源數(shù)模轉(zhuǎn)換器采用3mm DFN封裝】3毫米
文件頁(yè)數(shù)： 15/20頁(yè)
文件大小： 317K
代理商： LTC6078
LTC2641/LTC2642
15
26412f
APPLICATIONS INFORMATION
such as the LTC6078 is suitable, if the application does not
require linear operation very near to GND, or zero scale
(Figure 2). The LTC6078 typically swings to within 1mV
of GND if it is not required to sink any load current. For an
LSB size of 38μV, 1mV represents 26 missing codes near
zero scale. Linearity will be degraded over a somewhat
larger range of codes above GND. It is also unavoidable
that settling time and transient performance will degrade
whenever a single supply amplifier is operated very close
to GND, or to the positive supply rail.
The small LSB size of a 16-bit DAC, coupled with the tight
accuracy specifications on the LTC2641/LTC2642, means
that the accuracy and input specifications for the external
op amp are critical for overall DAC performance.
Op Amp Specifications and Unipolar DAC Accuracy
Most op amp accuracy specifications convert easily to
DAC accuracy.
Op amp input bias current on the noninverting (+) input is
equivalent to an I
L
loading the DAC V
OUT
pin and therefore
produces a DAC zero-scale error (ZSE) (see Unbuffered
Operation):
ZSE = –I
B
(IN+) R
OUT
[Volts]
In 16-bit LSBs:
( )
Op amp input impedance, R
IN
, is equivalent to an R
L
loading the LTC2641/LTC2642 V
OUT
pin, and produces a
gain error of:
k
k
R
IN
ZSE
I IN
B
–
k
k
V
LSB
REF
=
[
]
+
6 2
66
Op amp offset voltage, V
OS
, corresponds directly to DAC
zero code offset error, ZSE:
k
V
REF
Temperature effects also must be considered. Over the
–40°C to 85°C industrial temperature range, an offset
GE
LSB
[
=
+
]
–
.
66
6 2
1
ZSE
V
LSB
[
OS
=
]
66
voltage temperature coefficient (referenced to 25°C) of
0.6μV/°C will add 1LSB of zero-scale error. Also, I
BIAS
and
the V
OFFSET
error it causes, will typically show significant
relative variation over temperature.
Op amp open-loop gain, A
VOL
, contributes to DAC gain
error (GE):
k
A
VOL
Op amp input common mode rejection ratio (CMRR) is an
input-referred error that corresponds to a combination of
gain error (GE) and INL, depending on the op amp archi-
tecture and operating conditions. A conservative estimate
of total CMRR error is:
GE
LSB
[
=
]
66
where V
CMRR_RANGE
is the voltage range that CMRR (in
dB) is specified over. Op amp Typical Performance Charac-
teristics graphs are useful to predict the impact of CMRR
errors on DAC performance. Typically, a precision op amp
will exhibit a fairly linear CMRR behavior (corresponding
to DAC gain error only) over most of the common mode
input range (CMR), and become nonlinear and produce
significant errors near the edge of the CMR.
Rail-to-rail input op amps are a special case, because they
have 2 distinct input stages, one with CMR to GND and
the other with CMR to V
+
. This results in a “crossover”
CM input region where operation switches between the
two input stages.
The LTC6078 rail-to-rail input op amp typically exhibits
remarkably low crossover linearity error, as shown in the
V
OS
vs V
CM
Typical Performance Characteristics graphs
(see the LTC6078 data sheet). Crossover occurs at CM
inputs about 1V below V
+
, and an LTC6078 operating as
a unipolar DAC buffer with V
REF
= 2.5V and V
+
= 5V will
typically add only about 1LSB of GE and almost no INL
error due to CMRR. Even in a full rail-to-rail application,
with V
REF
= V
+
= 5V, a typical LTC6078 will add only about
1LSB of INL at 16-bits.
Error
V
V
CMRR
20
CMRR RANGE
_
RE
=
10
F
k LSB
]
66
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