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參數(shù)資料
| 型號： | LTC4268IDKD-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/46頁 |
| 文件大小： | 419K |
| 描述： | IC PD HIGH POWER W/CNTRL 32-DFN |
| 產(chǎn)品培訓(xùn)模塊： | Power over Ethernet |
| 標(biāo)準(zhǔn)包裝： | 52 |
| 類型： | 以太網(wǎng)供電開關(guān)（PoE） |
| 應(yīng)用： | 遠(yuǎn)程外設(shè)（工業(yè)控制，相機(jī)，數(shù)據(jù)訪問） |
| 內(nèi)部開關(guān)： | 是 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-DFN（7x4）裸露焊盤 |
| 包裝： | 管件 |
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LTC4268-1
10
42681fc
pin FuncTions
SHDN (Pin 1): Shutdown Input. Used to command the
LTC4268-1 to present an invalid signature and remain
inactive. Connecting SHDN to V
PORTP
lowers the signature
resistance to an invalid value and disables the LTC4268-1
PD interface operations. If unused, tie SHDN to V
PORTN
.
NC (Pin 2): No Internal Connection.
R
CLASS
(Pin 3): Class Select Input. Used to set the current
the LTC4268-1 maintains during classification. Connect a
resistor between R
CLASS
and V
PORTN
. (See Table 2.)
I
LIM_EN
(Pin 4): Input Current Limit Enable. Used for
controlling the LTC4268-1 current limit behavior during
powered operation. For normal operation, float I
LIM_EN
to
enable I
LIMIT_HIGH
current. Tie I
LIM_EN
to V
PORTN
to disable
input current limit. Note that the inrush current limit will
always be active. See Applications Information.
V
PORTN
(Pins 5, 6, 7): Power Input. Tie to the PD Input
through the diode bridge. Pins 5, 6 and 7 must be electri-
cally tied together.
NC (Pin 8): No Internal Connection.
SG (Pin 9): Secondary Gate Driver Output. This pin pro-
vides an output signal for a secondary-side synchronous
switch. Large dynamic currents may flow during voltage
transitions. See the Applications Information for details.
V
CC
(Pin 10): Converter Voltage Supply. Bypass this pin
to GND with 4.7礔 or greater. This pin has a 20V clamp
to ground. V
CC
has an undervoltage lockout function that
turns on when V
CC
is approximately 15.3V and off at 9.7V.
In a conventional trickle-charge bootstrapped configura-
tion, the V
CC
supply current increases significantly during
turn-on causing a benign relaxation oscillation action on
the V
CC
pin if the part does not start normally.
t
ON
(Pin 11): Primary Switch Minimum On Time Control.
A programming resistor (R
Ton
) to GND sets the minimum
time for each cycle. See Applications Information for details.
ENDLY (Pin 12): Enable Delay Time Control. The enable
delay time is set by a programming resistor (R
ENDLY
) to GND
and disables the feedback amplifier for a fixed time after
the turn-off of the primary-side MOSFET. This allows the
leakage inductance voltage spike to be ignored for flyback
voltage sensing. See Applications Information for details.
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to dis-
charge causing PG to go low (off) and SG high (on). The
sync threshold is typically 1.5V. Tie to ground if unused.
See Applications Information for details.
SFST (Pin 14): Soft-Start. This pin, in conjunction with a
capacitor (C
SFST
) to GND, controls the ramp-up of peak
primary current through the sense resistor. It is also used
to control converter inrush at start-up. The SFST clamps
the V
CMP
voltage and thus limits peak current until soft-
start is complete. The ramp time is approximately 70ms
per 礔 of capacitance. Leave SFST open if not using the
soft-start function.
OSC (Pin 15): Oscillator. This pin in conjunction with an
external capacitor (C
OSC
) to GND defines the controller
oscillator frequency. The frequency is approximately
100kHz " 100/C
OSC
(pF).
FB (Pin 16): Feedback Amplifier Input. Feedback is usually
sensed via a third winding and enabled during the flyback
period. This pin also sinks additional current to compensate
for load current variation as set by the R
CMP
pin. Keep the
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
V
CMP
(Pin 17): Frequency Compensation Control. V
CMP
is
used for frequency compensation of the switcher control
loop. It is the output of the feedback amplifier and the input
to the current comparator. Switcher frequency compensa-
tion components are normally placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback amplifier output is enabled
during the synchronous switch on time.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
from V
IN
to this pin sets an undervoltage lockout based
upon V
IN
level (not V
CC
). When the UVLO pin is below its
threshold, the gate drives are disabled, but the part draws
its normal quiescent current from V
CC
. The V
CC
undervolt-
age lockout supersedes this function so V
CC
must be great
enough to start the part. The bias current on this pin has
hysteresis such that the bias current is sourced when UVLO
threshold is exceeded. This introduces a hysteresis at the
pin equivalent to the bias current change times the imped-
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| LTC4269CDKD-1#PBF | 功能描述:IC PD/OPTO FLYBACK CTRLR 32-DFN RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 類型:熱交換控制器 應(yīng)用:-48V 遠(yuǎn)程電力系統(tǒng)，AdvancedTCA ? 系統(tǒng)，高可用性 內(nèi)部開關(guān):無 電流限制:可調(diào) 電源電壓:11.5 V ~ 14.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:10-MSOP 包裝:管件 |
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