參數(shù)資料
型號: LTC4257CS8
廠商: Linear Technology
文件頁數(shù): 15/20頁
文件大?。?/td> 263K
描述: IC CTRLR INTFACE PWR/ETHER 8SOIC
標準包裝: 100
類型: 以太網供電開關(PoE)
應用: IP 電話,LAN 網絡供電,網絡路由器和交換機
內部開關:
電流限制: 350mA
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 管件
產品目錄頁面: 1338 (CN2011-ZH PDF)
LTC4257
15
4257fb
Classification Resistor Selection (R
CLASS
)
IEEE 802.3af allows classifying PDs into four distinct
classes with class 4 being reserved for future use (Table 2).
An external resistor connected from R
CLASS
 to V
IN
 (Fig-
ure 3) sets the value of the classification current. The
designer should determine which power category the PD
falls into and then select the appropriate value of R
CLASS
from Table 2. If a unique classification current is required,
the value of R
CLASS
 can be calculated as:
R
CLASS
 = 1.237V/(I
DESIRED
  I
IN_CLASS
)
where I
IN_CLASS
 is the LTC4257 IC supply current during
classification and is given in the electrical specifications.
The R
CLASS
  resistor must be 1% or better to avoid
degrading the overall accuracy of the classification cir-
cuit. Resistor power dissipation will be 50mW maximum
and is transient so heating is typically not a concern. In
order to maintain loop stability, the layout should
minimize capacitance at the R
CLASS
 node. The classifica-
tion circuit can be disabled by floating the R
CLASS
 pin. The
R
CLASS
 pin should not be shorted to V
IN
 as this would
force the LTC4257 classification circuit to attempt to
source very large currents. In this case, the LTC4257 will
quickly go into thermal shutdown.
Power Good Interface
The PWRGD signal is controlled by a high voltage, open-
drain transistor. Examples of active-high and active-low
interface circuits for controlling the PD load are shown in
Figure 10.
In some applications it is desirable to ignore intermittent
power bad conditions. This can be accomplished by
including capacitor C15 in Figure 10 to form a lowpass
filter. With the components shown, power bad conditions
less than about 200祍 will be ignored. Conversely, in other
applications it may be desirable to delay assertion of
PWRGD to the PD load. The PWRGD signal can be delayed
with the addition of capacitor C17 in Figure 10.
APPLICATIO S I FOR ATIO
U
U
U
Figure 10. Power Good Interface Examples
GND
C1
5礔
100V
V
IN
8
4
48V
V
OUT
5
*C15 OPTIONAL TO FILTER PWRGD.
  SEE APPLICATIONS INFORMATION
LTC4257
PD
LOAD
SHDN
PWRGD
6
D6
5.1V
MMBZ5231B
C15*
0.047礔
10V
R9
100k
R9
100k
R18
10k
R18
10k
+
GND
C1
5礔
100V
Q1
FMMT2222
D6
MMBD4148
V
IN
8
4
48V
V
OUT
5
LTC4257
4257 F10
PD
LOAD
RUN
C17*
PWRGD
6
INTERNAL
PULLUP
+
ACTIVE-LOW ENABLE, 5.1V SWING
ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULLUP
TO
PSE
TO
PSE
C15*
0.047礔
10V
*C15 AND C17 OPTIONAL TO FILTER PWRGD.
  SEE APPLICATIONS INFORMATION
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LTC4257CS8#TRPBF 功能描述:IC CTRLR INTFACE PWR/ETHER 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 標準包裝:50 系列:- 類型:熱交換控制器 應用:-48V 遠程電力系統(tǒng),AdvancedTCA ? 系統(tǒng),高可用性 內部開關:無 電流限制:可調 電源電壓:11.5 V ~ 14.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP,10-MSOP(0.118",3.00mm 寬) 供應商設備封裝:10-MSOP 包裝:管件
LTC4257CS81 制造商:Linear Technology 功能描述: