- 您現(xiàn)在的位置：買賣IC網(wǎng) > Datasheet目錄42 > LTC4222CG#PBF (Linear Technology)IC CTRLR DUAL HOT SWAP 36-SSOP Datasheet資料下載
參數(shù)資料
| 型號： | LTC4222CG#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 339K |
| 描述： | IC CTRLR DUAL HOT SWAP 36-SSOP |
| 標準包裝： | 37 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 2.9 V ~ 29 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
LTC4222
16
4222fb
APPLICATIONS INFORMATION
Setting the CONFIG pin high allows the two channels to
start up and turn off independently. When both ON signals
are brought high sequentially, the channel turned on first
immediately begins to start up and the second channel
has a 200ns window to assert its ON signal in order to
start up in the same timer period. If the second ON signal
is asserted after the 200ns window but before the end of
the first channels start-up time, the second channel start-
up is delayed. The second channel will then start 100ms
after the first channels start-up timer has expired and the
TIMER pin, if used, reaches its 200mV low threshold.
When an external TIMER capacitor is used, the TIMER
capacitor voltage ramps up with a 100礎(chǔ) current. Once the
TIMER pin reaches its 1.235V threshold the TIMER begins
to discharge. While the TIMER capacitor is discharging, the
ON signal for the second channel should not be asserted
for 2ms/礔 of TIMER capacitance. This allows the TIMER
capacitor to return to its low state and ensures that the next
channel to start receives a full timer cycle. This wait time
is unnecessary when using the internal 100ms timer.
Board Present Change of State
The EN pins may be used to detect the presence of one or
two downstream cards. Whenever an EN pin toggles, FAULT
bit 4 is set to indicate a change of state. When the EN pin
goes high, indicating board removal, the corresponding
GATE turns off immediately (with a 1mA current to ground)
and the board present STATUS bit 4, is cleared. If the EN
pin is pulled low, indicating a board insertion, all fault bits
for that channel except FAULT bit 4 are cleared and enable
STATUS bit 4, is set. If the EN pin remains low for 100ms
the state of the ON pin is captured in FET On CONTROL
bit 3. This turns the switch on if the ON pin is tied high.
There is an internal 10礎(chǔ) pull-up current source on the
EN pin. If the CONFIG pin is tied low, both EN pins must
be low for 100ms for the two channels to be enabled and
if either EN pin goes high both channels will turn off.
If a channel shuts down due to a fault, it may be desirable
to restart that channel simply by removing and reinserting
the related load card. In cases where the LTC4222 and the
switch reside on a backplane or midplane and the load
resides on a plug-in card, the EN pin detects when the
plug-in card is removed. Figure 4 shows an example where
the EN pin is used to detect insertion. Once the plug-in card
is reinserted the fault register is cleared except for FAULT
bit 4. After 100ms the state of the ON pin is latched into
bit 3 of the CONTROL register. At this point the channel
starts up again.
If a connection sense on the plug-in card is driving an EN
pin, insertion or removal of the card may cause the pin
voltage to bounce. This results in clearing the fault register
when the card is removed. The pin may be debounced
using a filter capacitor, C
EN
, on the EN pin as shown in
Figure 4. The filter time is given by:
t
FILTER
= C
EN
" 123 (ms/礔)
Figure 4. Plug-In Card Insertion/Removal
+
1.235V
GND
MOTHERBOARD
CONNECTOR
PLUG-IN
CARD
SOURCE
OUT
LTC4222
10礎(chǔ)
EN
C
EN
LOAD
4222 F04
FET Short Fault
A FET short fault is reported if the data converter measures
a current sense voltage greater than or equal to 2mV while
the corresponding GATE is turned off. This condition sets
FET short bit, Fault bit 5.
Power-Bad Fault
A power-bad fault is reported if a FB pin voltage drops
below its 1.235V threshold for more than 2祍 when the
corresponding GATE is above the 4.3V gate to source
threshold. This pulls the GPIO pin low immediately in the
default power good configuration, and sets power-bad
present bit, STATUS bit 3, and power-bad bit, FAULT bit 3.
A circuit prevents power-bad faults if the GATE-to-SOURCE
voltage is low, eliminating false power-bad faults during
power-up or power-down. If the FB pin voltage subsequently
rises back above the threshold, a power good configured
GPIO pin returns to a high impedance state and STATUS
bit 3 is reset.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC4223CDHD-2#PBF | IC CNTRLR HOT SWAP DUAL 16-DFN |
| LTC4224IDDB-2#TRPBF | IC CNTRLR HOT SWAP DUAL 10-DFN |
| LTC4225IGN-1#PBF | IC CONTROLLER HOT SWAP 24-SSOP |
| LTC4230CGN#TRPBF | IC CONTRLLR HOT SWAP TRPL 20SSOP |
| LTC4232CDHC#TRPBF | IC CTLR HOT SWAP 5A 16-DFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC4222CG-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual Hot Swap Controller with I2C Compatible Monitoring |
| LTC4222CUH#PBF | 功能描述:IC CTRLR DUAL HOT SWAP 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:119 系列:- 類型:熱交換控制器 應(yīng)用:通用型，PCI Express? 內(nèi)部開關(guān):無 電流限制:- 電源電壓:3.3V，12V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-TQFP 供應(yīng)商設(shè)備封裝:80-TQFP（12x12） 包裝:托盤 產(chǎn)品目錄頁面:1423 (CN2011-ZH PDF) |
| LTC4222CUH#TRPBF | 功能描述:IC CTRLR DUAL HOT SWAP 32-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:119 系列:- 類型:熱交換控制器 應(yīng)用:通用型，PCI Express? 內(nèi)部開關(guān):無 電流限制:- 電源電壓:3.3V，12V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:80-TQFP 供應(yīng)商設(shè)備封裝:80-TQFP（12x12） 包裝:托盤 產(chǎn)品目錄頁面:1423 (CN2011-ZH PDF) |
| LTC4222CUH-PBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual Hot Swap Controller with I2C Compatible Monitoring |
| LTC4222CUH-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual Hot Swap Controller with I2C Compatible Monitoring |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。