Figure 5. Load Supply Power-Up Before VCC
參數(shù)資料
型號(hào)： LTC4213CDDB#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 0K
描述： IC CIRC BREAK ELEC 8-DFN
標(biāo)準(zhǔn)包裝： 2,500
系列： *
類(lèi)型： *
應(yīng)用： *
安裝類(lèi)型： 表面貼裝
封裝/外殼： 8-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 8-DFN（3x2）
包裝： 帶卷 (TR)
LTC4213
16
4213f
APPLICATIO S I FOR ATIO
WU
U
Figure 5. Load Supply Power-Up Before VCC
VON > 0.8V
Vth
01
2
3
4
5
6
7
8
VCC, VON
CIRCUIT BREAKER ARMS
READY SIGNALS
VREADY
VSENSEN
VSENSEP
RESET MODE
NORMAL CYCLE
tREADY
STARTUP CYCLE
tDEBOUNCE
VGATE
4213 F05
VSENSEP – VSENSEN = VCB
VGATE MAXES OUT
VCC > 2.07V
VGSARM + VSENSEN
VGSMAX + VSENSEN
Load Supply Power-Up Before VCC
Referring back to Figure 1, the VIN load supply can also be
powered up before VCC. Figure 5 shows the timing dia-
gram with the VIN load supply active initially. An internal
circuit ensures that the GATE pin is held low. At time point
1, VCC clears UVLO and at time point 2, ON clears 0.8V.
60s later at time point 3, the GATE is ramped up with
100A. At time point 4, GATE reaches the external MOSFET
threshold VTH and VOUT starts to ramp up. At time point 5,
VSENSEN is near its peak. At time point 6, the circuit breaker
is armed and the circuit breaker can trip if VSENSE > VCB.
At time point 7, the GATE voltage peaks. 50s after time
point 6, READY goes HIGH.
Startup Problems
There is no current limit monitoring during output charg-
ing for the figure 5 power-up sequence where the load
supply is powered up before VCC. This is because the GATE
voltage is below VGSARM and the MOSFET may not reach
the specified RDSON. The VIN load supply should have
sufficient capability to handle the inrush as the output
charges up. For proper startup, the final load at time
相關(guān)PDF資料
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DS2401Z+T&R IC SILICON SERIAL NUMBER SOT223
DS2401P+T&R IC SILICON SERIAL NUMBER 6-TSOC
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