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參數(shù)資料
| 型號(hào)： | LTC4212IMS#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 234K |
| 描述： | IC CTRLR HOTSWAP TIMEOUT 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 2.5 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
12
LTC4212
4212f
Since the PGT is pulled to GND by M12 before the power
good circuit is enabled, the first positive ramp at the PGT
pin starts from 0V instead of the 0.65V for the subsequent
13 cycles.
Power Good Time-Out
At the end of the time-out period, the PGI pin is sampled.
M12 is turned on to discharge C
PGT
to ground. If the PGI
pin is low when sampled, the DC/DC converters have not
entered into regulation on time and the power good circuit
trips the circuit breaker to latch off the board. If PGI is high
when sampled, the converters powered up into regulation
on time and the board is left powered up. The power good
glitch filter is enabled and it monitors the PGI pin for a low,
an indication that at least one DC/DC converter has dropped
out of regulation. The glitch filter rejects low pulses
shorter than a programmable period.
Power Good Glitch Filter
A glitch filter consisting of COMP5, M5 and a 5礎(chǔ) current
source rejects PGI low pulses that are shorter than the
duration programmed by an external capacitor, C
PGF
,
connected from the PGF pin to GND.
Once the glitch filter is enabled, M5 is switched off
whenever PGI goes low. This allows an internal 5礎(chǔ)
current source to charge the capacitor at the PGF pin. If
PGI stays low for long enough, the voltage at the PGF pin
rises above the upper threshold of COMP5 (1.236V) and
causes the power good circuit to trip the circuit breaker.
For a given C
PGF
capacitance connected between PGF and
GND, the minimum low PGI pulse width needed to trip the
circuit breaker is given by:
t
PGF
= 1.236V " (C
PGF
)/5礎(chǔ) + 5祍
(4)
An internal 5pF capacitor and stray MSOP-10 package
capacitance sets t
PGF
to 5祍 nominal when C
PGF
is omit-
ted. Table 3 shows t
PGF
values for various standard
capacitors. Tying the PGF pin to ground prevents the
power good glitch filter from tripping the circuit breaker
after normal power-up.
OPERATIO
Table 3. t
PGF
vs C
PGF
C
PGF
t
PGF
5祍
10pF
7.5祍
22pF
10.4祍
33pF
13.2祍
47pF
16.6祍
68pF
21.8祍
82pF
25.2祍
100pF
29.7祍
220pF
59.3祍
330pF
86.6祍
470pF
121.2祍
680pF
173祍
820pF
208祍
1nF
252祍
Soft-Start or Inrush Current Control
The LTC4212 monitors the load current by sensing the
voltage (V
CC
V
SENSE
) developed across an external
sense resistor (R
SENSE
) connected between the V
CC
and
SENSE pins. During the second timing cycle (see Normal
Operating Sequence) a soft-start circuit turns on the
external N-channel FET gradually to keep inrush currents
in check. The soft-start circuit monitors and servos the
voltage across R
SENSE
to 50mV by either connecting a
10礎(chǔ) pull-up current source to the GATE pin when the
voltage across R
SENSE
is less than 50mV or discharging it
with a 10礎(chǔ) pull-down current source when the voltage
rises above 50mV. Therefore, the inrush current from the
backplane supply is limited to:
I
LIMIT(SOFTSTART)
= 50mV/R
SENSE
(5)
For example, I
LIMIT(SOFTSTART)
= 5A when R
SENSE
= 0.01&.
Assuming that the voltage across the sense resistor does
not exceed 50mV, the voltage at the GATE pin rises at rate
given by:
V
GATE
Slew Rate = dV
GATE
/dt =10礎(chǔ)/C
GATE
(6)
where, C
GATE
= Power MOSFET gate input capacitance
(C
ISS
).
For example, an Si4410DY (a 30V N-channel power
MOSFET) exhibits an approximate C
GATE
of 3300pF at
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