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參數(shù)資料
| 型號： | LTC4212IMS#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 234K |
| 描述： | IC CTRLR HOTSWAP TIMEOUT 10MSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 2.5 V ~ 16.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
11
LTC4212
4212f
set C
TIMER
= 10nF and adjust its value accordingly to suit
the specific applications.
Table 1. t
TIMER
vs C
TIMER
C
TIMER
t
TIMER
0.0033礔
2.0ms
0.0047礔
2.9ms
0.0068礔
4.2ms
0.0082礔
5.1ms
0.01礔
6.2ms
0.015礔
9.3ms
0.022礔
13.6ms
0.033礔
20.4ms
0.047礔
29.0ms
0.068礔
42.0ms
0.082礔
50.7ms
0.1礔
61.8ms
0.15礔
92.7ms
0.22礔
136ms
0.33礔
204ms
Power-Up Timeout Circuit
The power-up timeout circuit has two functions. During
power-up, it trips the circuit breaker if the DC/DC convert-
ers on the board do not power-up and do not enter
regulation on time. After normal power-up, it is configured
to trip the circuit breaker if any of the converters exit
regulation for longer than a programmable delay. Once the
circuit breaker is tripped, the LTC4212 is latched off and
the board is disconnected from the system supply. The ON
pin must be taken low for 120祍 to reset the circuit breaker
and then high to reconnect the board to the backplane
supply.
The power-up timeout circuit uses three pins: PGI or
power good input pin, PGT or power good timer pin and
PGF or power good filter pin. It is enabled at the end of the
second system timing cycle, provided that the FAULT pin
is high. Prior to being enabled or if FAULT is low, the PGT
and PGF pins are pulled to GND by internal N-channel
FETs, M5 and M12 respectively. When enabled, the
power-up timeout circuit starts the power good timer,
which generates a time-out period before the PGI pin is
sampled.
OPERATIO
Power Good Timer
The timer consists of COMP9, M8-M12, two 5礎(chǔ) current
sources and 0.65V and 0.95V threshold voltages for
COMP9.
The PGI pin is normally connected to the RST output pin
or comparator outputs of an external supply monitor IC or
to the PGOOD pin of a DC/DC converter and drives a
comparator, COMP8 which has a threshold voltage of
1.236V and 28mV of hysterisis. The RST and PGOOD pins
are typically open drain pins and require an external pull-
up resistor. The upper end of the resistor must be con-
nected to a voltage greater than the upper threshold of the
PGI comparator (1.236V).
A capacitor, C
PGT
, connected from the PGT pin to ground
programs the time-out period generated by the power
good timer according to Equation 3. Table 2 shows the
power good time-out periods for a list of standard capaci-
tor values.
t
TIMEOUT
= 1.81& " C
PGT
(3)
Two 5礎(chǔ) current sources are switched in and out to charge
and discharge C
PGT
between 0.65V and 0.95V for 14
cycles.
Table 2. t
TIMEOUT
vs C
PGT
C
PGT
t
TIMEOUT
3.3nF
5.97ms
4.7nF
8.51ms
6.8nF
12.3ms
8.2nF
14.8ms
0.01礔
18.1ms
0.022礔
39.8ms
0.033礔
59.7ms
0.047礔
85.1ms
0.068礔
123ms
0.082礔
148ms
0.1礔
181ms
0.22礔
136ms
0.33礔
398ms
0.47礔
851ms
0.68礔
1230ms
0.82礔
1480ms
1礔
1810ms
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