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參數(shù)資料
| 型號(hào)： | LTC4000EUFD#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQCC28 |
| 封裝： | 4 X 5 MM, LEAD FREE, PLASTIC, MO-220WXXX-X, QFN-28 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 428K |
| 代理商： | LTC4000EUFD#PBF |
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LTC4000
17
4000f
Input Ideal Diode PMOS Selection
TheinputexternalPMOSisselectedbasedontheexpected
maximum current, power dissipation and reverse volt-
age drop. The PMOS must be able to withstand a gate to
source voltage greater than VIGATE(ON) (15V maximum) or
the maximum regulated voltage at the IID pin, whichever
is less. A few appropriate external PMOS for a number of
different requirements are shown at Table 1.
Table 1. PMOS
PART NUMBER
RDS(ON) AT
VGS = 10V
(Ω)
MAX ID
(A)
MAX VDS
(V)
MANUFACTURER
SiA923EDJ
0.054
4.5
–20
Vishay
Si9407BDY
0.120
4.7
–60
Vishay
Si4401BDY
0.014
10.5
–40
Vishay
Si4435DDY
0.024
11.4
–30
Vishay
SUD19P06-60
0.060
18.3
–60
Vishay
Si7135DP
0.004
60
–30
Vishay
Note that in general the larger the capacitance seen on
the IGATE pin, the slower the response of the ideal diode
driver. The fast turn off and turn on current is limited to
–0.5mAand0.7mAtypicalrespectively(IIGATE(FASTOFF)and
IIGATE(FASTON)). If the driver can not react fast enough to a
sudden increase in load current, most of the extra current
is delivered through the body diode of the external PMOS.
This increases the power dissipation momentarily. It is
important to ensure that the PMOS is able to withstand
this momentary increase in power dissipation.
Input Current Limit Setting and Monitoring
The regulated input current limit is set using a resistor at
the IL pin according to the following formula:
RIS =
VIL
20 IILIM
whereVIListhevoltageontheILpin.TheILpinisinternally
pulledupwithanaccuratecurrentsourceof50A.Therefore
an equivalent formula to obtain the input current limit is:
RIL =
ILIM RIS
2.5A
IILIM =
RIL
RIS
2.5A
applicaTions inForMaTion
The input current through the sense resistor is available
for monitoring through the IIMON pin. The voltage on
the IIMON pin varies with the current through the sense
resistor as follows:
VIIMON = 20 IRIS RIS = 20 VIN – VCLN
(
)
The regulation voltage level at the IIMON pin is clamped
at 1V with an accurate internal reference. At 1V on the
IIMON pin, the input current limit is regulated at the fol-
lowing value:
IILIM(MAX)(A) =
0.050V
RIS(Ω)
When this maximum current limit is desired, leave the IL
pin open or set it to a voltage >1.05V such that amplifier
A4canregulatetheIIMONvoltageaccuratelytotheinternal
reference of 1V.
If the input current is noisy, add a filter capacitor to the
CLN pin to reduce the AC content. For example, when us-
ing a buck DC/DC converter, the use of a CCLN capacitor
is strongly recommended. Where the highest accuracy is
important, pick the value of CCLN such that the AC content
is less than or equal to 50% of the average voltage across
the sense resistor.
The voltage on the IIMON pin can be filtered further by
putting a capacitor on the pin (CIIMON). The voltage on the
IIMON pin is also the feedback input to the input current
regulation error amplifier. Any capacitor connected to
this pin places a pole in the input current regulation loop.
Therefore, this filter capacitor should NOT be arbitrarily
large as it will slow down the overall compensated loop.
For details on loop compensation please refer to the
Compensation section.
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