參數(shù)資料
型號(hào): LTC3880IUJ#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.1 A DUAL SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC40
封裝: 6 X 6 MM, LEAD FREE, PLASTIC, WJJD-2, QFN-40
文件頁數(shù): 55/112頁
文件大?。?/td> 2182K
代理商: LTC3880IUJ#PBF
LTC3880/LTC3880-1
47
3880fa
APPLICATIONS INFORMATION
If the LTC3880 internal temperature is in excess of 85°C,
the write into the NVM is not recommended. The data will
still be held in RAM, unless the 3.3V supply UVLO thresh-
old is reached. If the die temperature exceeds 130°C all
NVM communication is disabled until the die temperature
drops below 120°C.
OPEN-DRAIN PINS
The LTC3880 has the following open-drain pins:
3.3V Pins
1. GPIOn
2. SYNC
3. SHARE_CLK
5V Pins (5V pins operate correctly when pulled to 3.3V.)
1. RUNn
2. ALERT
3. SCL
4. SDA
All the above pins have on-chip pull-down transistors
that can sink 3mA at 0.4V. The low threshold on the pins
is 1.4V; thus, plenty of margin on the digital signals with
3mA of current. For 3.3V pins, 3mA of current is a 1.1k
resistor. Unless there are transient speed issues associ-
ated with the RC time constant of the resistor pull-up and
parasitic capacitance to ground, a 10k resistor or larger
is generally recommended.
For high speed signals such as the SDA, SCL and SYNC,
a lower value resistor may be required. The RC time con-
stant should be set to 1/3 to 1/5 the clocking frequency
to avoid timing issues. For a 100pF load and a 400kHz
PMBus communication rate, the resistor pull-up on the
SDA and SCL pins with the time constant set to 3 times
the clock rate equals:
RPULLUP =
1
400kHz 3 100pF
= 8.33k
The closest 1% resistor value is 8.25k. Be careful to
minimize parasitic capacitance on the SDA and SCL
pins to avoid communication problems. To estimate the
loading capacitance, monitor the signal in question and
measure how long it takes for the desired signal to reach
approximately 63% of the output value. This is one time
constant.
The SYNC pin has an on-chip pull-down transistor with
the output held low for nominally 500ns. If the internal
oscillator is set for 500kHz and the load is 100pF and a
3x time constant is required, the resistor calculation is
as follows:
RPULLUP =
2s – 500ns
3 100pF
= 5k
The closest 1% resistor is 4.99k.
If timing errors are occurring or if the SYNC frequency is
notasfastasdesired,monitorthewaveformanddetermine
if the RC time constant is too long for the application. If
possiblereducetheparasiticcapacitance.Ifnotreducethe
pull up resistor sufficiently to assure proper timing.
PHASE-LOCKED LOOP AND FREQUENCY
SYNCHRONIZATION
The LTC3880 has a phase-locked loop (PLL) comprised of
aninternalvoltage-controlledoscillator(VCO)andaphase
detector. The PLL is locked to the falling edge of the SYNC
pin. The phase relationship between channel 0, channel 1
and the falling edge of SYNC is controlled by the lower 3
bits of the MFR_PWM_CONFIG_LTC3880 command. For
PolyPhase applications, it is recommended all the phases
be spaced evenly. Thus for a 2-phase system the signals
should be 180° out of phase and a 4-phase system should
be spaced 90°.
The phase detector is an edge-sensitive digital type that
provides a known phase shift between the external and
internal oscillators. This type of phase detector does not
exhibit false lock to harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the internal
filter network. The PLL lock range is guaranteed between
250kHz and 1MHz. Nominal parts will have a range beyond
this; however, operation to a wider frequency range is not
guaranteed.
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