參數(shù)資料
型號(hào)： LTC3823IGN#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： 穩(wěn)壓器
英文描述： 4 A SWITCHING CONTROLLER, PDSO28
封裝： 0.150 INCH, LEAD FREE, PLASTIC, SSOP-28
文件頁(yè)數(shù)： 13/26頁(yè)
文件大?。?/td> 302K
代理商： LTC3823IGN#TRPBF
LTC3823
20
3823fd
APPLICATIONS INFORMATION
Design Example
As a design example, take a supply with the following
specications: VIN = 5V to 28V (15V nominal), VOUT =
2.5V ±5%, IOUT(MAX) = 10A, f = 320kHz. First, calculate
the timing resistor with VON = VOUT:
R
V
VkHz
pF
k
ON =
()(
)( )
=
25
3 2 5
320
10
104
.
Ω
and choose the inductor for about 40% ripple current at
the maximum VIN:
L
V
kHz
A
V
= ()( )( )
=
25
320
0 4 10
1
25
28
17
.
.7
7H
Selecting a standard value of 1.2μH results in a maximum
ripple current of:
Δ
μ
I
V
kHz
H
V
A
L =
()(
)
=
25
320
1 2
1
25
28
59
.
–
.
Next, choose the synchronous MOSFET switch. Choosing
a Si7892ADP (RDS(ON) = 0.005Ω (NOM) 0.006Ω (MAX),
θJA = 50°C/W) yields a nominal sense voltage of:
VSNS(NOM) = (7A)(1.3)(0.005Ω) = 45mV
Tying VRNG to0.75Vwillsetthecurrentsensevoltagerange
for a nominal value of 75mV with current limit occurring
at 100mV. To check if the current limit is acceptable, as-
sume a junction temperature of about 80°C above a 70°C
ambient with
ρ150°C = 1.5:
I
mV
AA
LIMIT ≥
()(
)
+
() =
100
15 0006
1
2
59
14
..
.
Ω
and double check the assumed TJ in the MOSFET:
P
VV
V
AW
BOT =
() ( )(
) =
28
25
28
14
15 0 006
16
2
–.
..
.
Ω
TJ = 70°C + (1.6W)(50°C/W) = 150°C
Because the top MOSFET is on for such a short time,
an Si7342DP RDS(ON)(MAX) = 0.010Ω, CRSS = 120pF,
θJA=53°C/Wwillbesufcient.Checkingitspowerdissipa-
tion at current limit with
ρ100°C=1.4:
P
V
A
V
TOP =
() ( )
Ω
()+
()( )
25
28
14
1 4 0 010
17 28
2
.
..
.1
14
120
320
025
0 72
097
ApF
kHz
WW
W
()(
)(
)
=+=
..
.
TJ = 70°C + (0.97W)(53°C/W) = 121°C
The junction temperature will be signicantly less at
nominal current, but this analysis shows that careful at-
tention to heat sinking on the board will be necessary in
this circuit.
CIN is chosen for an RMS current rating of about 3A at
85°C. The output capacitors are chosen for a low ESR
of 0.013Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
ΔVOUT(RIPPLE) = ΔIL(MAX) (ESR)
= (5.9A) (0.013Ω) = 77mV
However, a 0A to 10A load step will cause an output
change of up to:
ΔVOUT(STEP) = ΔILOAD (ESR) = (10A) (0.013Ω) = 130mV
An optional 22μF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 12.
PC Board Layout Checklist
When laying out a PC board follow one of two suggested
approaches. The simple PC board layout requires a ded-
icated ground plane layer. Also, for higher currents, it is
recommended to use a multilayer board to help with heat
sinking power components.
The ground plane layer should not have any traces and
it should be as close as possible to the layer with power
MOSFETs.
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PDF描述
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