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參數資料
| 型號： | LTC3809EMS#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1 A SWITCHING CONTROLLER, 825 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | PLASTIC, MSOP-10 |
| 文件頁數： | 8/24頁 |
| 文件大?。?/td> | 266K |
| 代理商： | LTC3809EMS#PBF |
16
LTC3809
3809f
is an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
MODE, is shown in Figure 5 and specified in the electrical
characteristics table. Note that the LTC3809 can only be
synchronized to an external clock whose frequency is within
range of the LTC3809’s internal VCO, which is nominally
200kHz to 1MHz. This is guaranteed, over temperature and
process variations, to be between 250kHz and 750kHz. A
simplified block diagram is shown in Figure 6.
APPLICATIO S I FOR ATIO
WU
UU
LTC3809
VFB
VOUT
RB
CFF
RA
3809 F03
Figure 3. Setting Output Voltage
For most applications, a 59k resistor is suggested for RA.
In applications where minimizing the quiescent current is
critical, RA should be made bigger to limit the feedback
divider current. If RB then results in very high impedance,
it may be beneficial to bypass RB with a 50pF to 100pF
capacitor CFF.
Run and Soft-Start Functions
The LTC3809 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 1.1V
puts the LTC3809 into a low quiescent current shutdown
mode (IQ = 9A). Releasing the RUN pin, an internal 0.7A
(at VIN = 4.2V) current source will pull the RUN pin up to
VIN, which enables the controller. The RUN pin can be
driven directly from logic as showed in Figure 4.
Once the controller is enabled, the start-up of VOUT is
controlled by the internal soft-start, which slowly ramps
the positive reference to the error amplifier from 0V to
0.6V, allowing VOUT to rise smoothly from 0V to its final
value. The default internal soft-start time is around 1ms.
3.3V OR 5V
3809 F04
LTC3809
RUN
LTC3809
RUN
Figure 4. RUN Pin Interfacing
Phase-Locked Loop and Frequency Synchronization
The LTC3809 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the external P-channel
MOSFET to be locked to the rising edge of an external clock
signal applied to the SYNC/MODE pin. The phase detector
Figure 6. Phase-Locked Loop Block Diagram
Figure 5. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
PLLLPF PIN VOLTAGE (V)
0.2
0
FREQUENCY
(kHz)
0.7
1.2
1.7
3809 F05
2.2
200
400
600
800
1000
1200
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
RLP
CLP
3809 F06
PLLLPF
EXTERNAL
OSCILLATOR
SYNC/
MODE
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