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參數(shù)資料
| 型號： | LTC3783IDHD |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 1 A SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | 5 X 4MM, PLASTIC, MO-229WJGD-2, DFN-16 |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 250K |
| 代理商： | LTC3783IDHD |
LTC3783
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3783fb
PIN FUNCTIONS
FBN (Pin 1): Error Amplier Inverting Input/Negative Cur-
rent Sense Pin. In voltage mode (VFBP ≤ VVREF), this pin
senses feedback voltage from either the external resistor
divider across VOUT for output voltage regulation, or the
grounded sense resistor under the load for output current
regulation. In constant current/constant voltage mode
(VFBP > 2.5V), connect this pin to the negative side of the
current-regulating resistor. Nominal voltage for this pin in
regulation is either VFBPor(VFBP–100mV)forVILIM= 1.23V,
depending on operational mode (voltage or constant cur-
rent/constant voltage) set by the voltage at VFBP.
FBP (Pin 2): Error Amplier Noninverting Input/Positive
Current Sense Pin. This pin voltage determines the control
loop’s feedback mode (voltage or constant current/constant
voltage), the threshold of which is approximately 2V. In
voltage mode (VFBP ≤ VREF), this pin represents the desired
voltage which the regulated loop will cause FBN to follow.
In constant current/constant voltage mode (VFBP > 2.5V),
connect this pin to the positive side of the load current-
sensing resistor. The acceptable input ranges for this pin
are 0V to 1.23V (voltage mode) and 2.5V to 36V (constant
current/constant voltage mode).
ILIM(Pin 3): Current Limit Pin. Sets current sense resis-
tor offset voltage (VFBP – VFBN) in constant current mode
regulation (i.e., when VFBP > 2.5V). Offset voltage is 100mV
when VILIM=1.23VanddecreasesproportionallywithVILIM.
Nominal voltage range for this pin is 0.1V to 1.23V.
VREF (PIN 4): Reference Voltage Pin. Provides a buffered
version of the internal bandgap voltage, which can be
connected to FBP either directly or with attenuation.
Nominal voltage for this pin is 1.23V. This pin should
never be bypassed by a capacitor to GND. Instead, a 10k
resistor to GND should be used to lower pin impedance
in noisy systems.
FREQ (Pin 5): A resistor from the FREQ pin to ground
programs the operating frequency of the chip. The nominal
voltage at the FREQ pin is 0.615V.
SYNC (Pin 6): This input allows for synchronizing the op-
erating frequency to an external clock and has an internal
100k pull-down resistor.
PWMIN (Pin 7): PWM Gate Driver Input. Internal 100k
pull-up resistor. While PWMIN is low, PWMOUT is low,
GATE stops switching and the external ITH network is
disconnected, saving the ITH state.
PWMOUT (Pin 8): PWM Gate Driver Output. Used for con-
stant current dimming (LED load) or for output disconnect
(step-up power supply).
GATE (Pin 9): Main Gate Driver Output for the Boost
Converter.
INTVCC (Pin 10): Internal 7V Regulator Output. The main
and PWM gate drivers and control circuits are powered
from this voltage. Decouple this pin locally to the IC ground
with a minimum of 4.7μF low ESR ceramic capacitor.
VIN (Pin 11): Main Supply Pin. Must be closely decoupled
to ground.
SENSE (Pin 12): Current Sense Input for the Control Loop.
Connect this pin to the drain of the main power MOSFET
for VDS sensing and highest efciency for VSENSE ≤ 36V.
Alternatively, the SENSE pin may be connected to a resistor
in the source of the main power MOSFET. Internal leading-
edge blanking is provided for both sensing methods.
SS (Pin 13): Soft-Start Pin. Provides a 50μA pull-up current,
enabledandresetbyRUN,whichchargesanoptionalexternal
capacitor. This voltage ramp translates into a corresponding
current limit ramp through the main MOSFET.
OV/FB (Pin 14): Overvoltage Pin/Voltage Feedback Pin.
In voltage mode (VFBP ≤ VREF), this input, connected to
VOUT through a resistor network, sets the output voltage
at which GATE switching is disabled in order to prevent
an overvoltage situation. Nominal threshold voltage for
the OV pin is 1.32V (VREF + 7%) with 20mV hysteresis. In
current/voltage mode (VFBP > 2.5V), this pin senses VOUT
through a resistor divider and brings the loop into voltage
regulation such that pin voltage approaches VREF = 1.23V,
provided the loop is not regulating the load current (e.g.,
[VFBP – VFBN] < 100mV for ILIM = 1.23V).
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