參數(shù)資料
型號(hào): LTC3765IMSE#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封裝: LEAD FREE, PLASTIC, MSOP-16
文件頁(yè)數(shù): 9/24頁(yè)
文件大?。?/td> 265K
代理商: LTC3765IMSE#TRPBF
LTC3765
17
3765f
APPLICATIONS INFORMATION
A lower bound on the primary-side soft-start capacitor
(CSS) value was previously calculated in the overcurrent
sectiontoensurethattheovercurrentcomparatordoesnot
trip on start-up into a full load. The value should generally
be in the range of 10nF to 1F. Choosing too small of a
value for CSS could potentially charge the output voltage
too quickly at no load or cause an overcurrent trip when
starting into full load. Choosing too large a value will cre-
ate additional delay in the start-up, during which time the
linear regulator will be providing the current to switch the
primary NMOS. Extremely long start-up times should be
avoided to avoid excessive power dissipation in the linear
regulator pass device. A value of 33nF is a good starting
point for most applications.
Thesoft-startcapacitorvalueshouldbeverifiedbycompar-
ing the time for the peak charge circuit to deliver adequate
biastotheLTC3766tothetimethattheoutputvoltagerises
to half of its regulated value. The time until the LTC3766
receives bias and takes control can be approximated by:
tBIAS ≈10
3 R
EQ CPK CSS + 150s
where REQ is the sum of RPK and the series resistance
of diode DPK.
The time for the output voltage to reach half of its regulated
value can then be estimated by the following equation,
where VOUT is the final regulated output voltage:
tOUT ≈10
4
CSS2 VOUT/ 2
(
)2LCOUT fSW
VIN(MIN) NS/NP
(
)2
1/3
The above equation assumes that there is no load cur-
rent, which is the worst-case condition for output voltage
rise. If tOUT is less than tBIAS, then the soft-start capacitor
value should be increased. Note that these equations are
approximations and the actual times will vary somewhat
with circuit parameters.
Gate Drivers
The active clamp gate driver (AG) and the primary switch
gate driver (PG) are “in-phase,” with a programmable
overlap time set by the DELAY pin. Traditionally in active
clampdrivers,theAGdrivermustbelevel-shiftedasshown
in the circuit in Figure 7a to drive the active clamp PMOS
gate from approximately VD to –VCC + VD, where VD is
the forward voltage drop across the Schottky diode DAG.
A silicon diode can be used instead of a Schottky barrier
diode; however, the forward voltage of the diode does
subtract from the available gate drive of the active clamp
PMOS. This is particularly important at the minimum VCC
UVLO falling threshold.
Theresistor,RAG,ensuresthattheactiveclampPMOSisoff
when not being driven. The active clamp level-shift circuit
components can be chosen with few constraints. The time
constant formed by RAG and CAG should be designed to
be substantially longer than the switching period of the
controller. A 0.1F capacitor for CAG and a 10k resistor for
RAG result in a 1ms time constant, which provides suf-
ficient margin for the 75kHz to 500kHz frequency range
available in the LTC3766.
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