參數(shù)資料
型號: LTC3765IMSE#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO16
封裝: LEAD FREE, PLASTIC, MSOP-16
文件頁數(shù): 21/24頁
文件大?。?/td> 265K
代理商: LTC3765IMSE#TRPBF
LTC3765
6
3765f
PIN FUNCTIONS
PGND (Pin 1): Power Ground. Ground return for the high
current gate drivers.
PG (Pin 2): Primary Gate. Gate drive for the primary
switch NMOS.
VCC (Pin 3): Main Supply Pin. A ceramic bypass capacitor
should be tied between this pin and ground.
AG (Pin 4): Active Gate. Gate drive for the active clamp
PMOS. This drive output is “in phase” with the PG out-
put. Connect to the gate of a PMOS through a capacitive
level-shift circuit.
ISMAG (Pin 5): Magnetizing Current Sense Pin. Connect
to a current sense resistor in series with the source of
the active clamp PMOS. This pin limits the magnetizing
current of the main transformer to prevent core saturation
when the active clamp is on.
DELAY (Pin 6): Primary Gate Rising Delay Adjustment. A
resistor from this pin to ground sets the AG rising to PG
rising dead time, which is critical for optimizing efficiency.
IS–, IS+ (Pin 7, Pin 8): Inputs to the Overcurrent Compara-
tor. Connect across a current sense resistor in series with
the source of the primary NMOS.
FS/UV(Pin10):OscillatorFrequencySetandUndervoltage
Indicator.Aresistortogroundsetstheswitchingfrequency
during start-up. When the RUN pin is low, the VCC sup-
ply is undervoltage, or the overtemperature protection is
active, a 50A current source pulls this pin to the lesser
of VCC and 5V as an indicator.
RCORE (Pin 11): Transformer Core Saturation Limit. A
resistorfromRCOREtogroundproportionaltotransformer
core parameters internally replicates the magnetizing cur-
rent slope when the primary NMOS is on. This slope in
combination with the voltage on the ISMAG and RUN pins
limits the on-time of the NMOS to prevent saturation. See
Applications Information.
RUN (Pin 12): Run Control and Undervoltage Lockout
(UVLO). Connect to a resistor divider to monitor the input
voltage VIN, which is required for proper operation of
the Direct Flux Limit. Converter operation is enabled for
VRUN>1.25V.Hysteresisisafixed50mVwithanadditional
5A hysteresis current that combines with the resistor
divider to comprise the total UVLO hysteresis voltage.
SSFLT(Pin13):CombinationSoft-StartandFaultIndicator.
A capacitor to ground sets the duty cycle ramp-up rate
during primary-side start-up. To indicate a fault, the SSFLT
pin is momentarily pulled above 6V.
NDRV (Pin 14): Drive for External Linear Regulator. Con-
nect to the gate of an NMOS and connect a pull-up resistor
to the main input voltage, VIN. An internal charge pump
drivesthispinaboveVINforlowinputvoltageapplications.
IN+, IN(Pin 15, Pin 16): Inputs from Pulse Transformer.
Connect through a DC restoring capacitor to the output
winding of a pulse transformer. The input winding of the
pulsetransformerisdrivenbytheLTC3766.Afterperform-
ing an initial open-loop start-up, the LTC3765 detects and
decodes pulse encoded PWM information at these pins,
and then turns control of the PG and AG switching over
to the LTC3766 secondary-side controller. Additionally,
an internal bridge rectifier on the IN+/INpins extracts
DC power from the pulse transformer and delivers it to
the VCC pin.
SGND (Pin 9, Exposed Pad Pin 17): Signal Ground. The
exposed pad metal of the package provides good thermal
contact to the printed circuit board. It must be soldered to
a ground plane for rated thermal performance.
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