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參數(shù)資料
| 型號(hào)： | LTC3672BEDC-2#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | 1.1 A SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO8 |
| 封裝： | 2 X 2 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, DFN-8 |
| 文件頁(yè)數(shù)： | 9/12頁(yè) |
| 文件大?。?/td> | 165K |
| 代理商： | LTC3672BEDC-2#PBF |
LTC3672B-2
6
3672b2fa
BLOCK DIAGRAM
PIN FUNCTIONS
SW (Pin 1): Switch Node Connection to Inductor. This pin
connects to the drains of the buck regulator’s main PMOS
and synchronous NMOS switches.
GND (Pin 2): Ground.
ENALL (Pin 3): Enables all three outputs when high, shuts
down the IC when low. This is a MOS gate input. An internal
5.5M
Ω resistor pulls this pin to ground.
BUCKOUT (Pin 4): Output Voltage Sense Connection for
the Buck Regulator.
VIN1 (Pin 5): Power Input for the First Low Dropout Linear
Regulator, LDO1. This pin may be connected to VIN (Pin 8),
or to a voltage never exceeding VIN.
LDO1 (Pin 6): Output of the First Low Dropout Linear
Regulator. This pin must be bypassed to ground with a
1μF or greater ceramic capacitor.
LDO2 (Pin 7): Output of the Second Low Dropout Linear
Regulator. This pin must be bypassed to ground with a
1μF or greater ceramic capacitor.
VIN (Pin 8): Input Bias Supply for the IC, and Power
Input for the Buck Regulator and LDO2. This pin should
be bypassed to ground with a 2.2μF or greater ceramic
capacitor.
Exposed Pad (Pin 9): Ground. The Exposed Pad must be
soldered to PCB ground.
5.5M
LDO1
3672B2 BD
800k
6
LDO2
7
SW
1
BUCKOUT
400mA BUCK
4
VIN
8
VIN1
5
GND
2
EXPOSED PAD (GND)
9
ENALL
3
2M
800k
1M
800k
400k
LDO1
+
–
LDO2
LOGIC
ENABLE LDO2
ENABLE
BUCK
ENABLE LDO1
2.25MHz
OSC
800mV
REFERENCE
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