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參數(shù)資料
| 型號(hào)： | LTC3625IDE-1#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO12 |
| 封裝： | 3 X 4 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, MO-229WGED, DFN-12 |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 262K |
| 代理商： | LTC3625IDE-1#PBF |
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LTC3625/LTC3625-1
3625f
applicaTions inForMaTion
board ground. Failure to make thermal contact between
the exposed pad on the backside of the package and the
copper board will result in higher thermal resistances.
Furthermore, due to its potentially high frequency switch-
ing circuitry, it is imperative that the input capacitor,
inductors, and output bypass capacitors be as close to
the LTC3625/LTC3625-1 as possible, and that there be an
unbroken ground plane under the IC and all of its external
highfrequencycomponents.Highfrequencycurrents,such
as the VIN and VOUT currents on the LTC3625/LTC3625-1,
tend to find their way along the ground plane in a myriad of
paths ranging from directly back to a mirror path beneath
the incident path on the top of the board. If there are slits or
cuts in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to flow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. There should be a
group of vias under the grounded backside of the pack-
age leading directly down to an internal ground plane. To
minimize parasitic inductance, the ground plane should
be on the highest possible layer of the PC board.
Any board resistance between inductor(s) and the posi-
tive terminal of CBOT will add to the capacitors internal
ESR. Likewise, any resistance between the VOUT pin
and the positive terminal of CTOP will add to its internal
ESR. Any added resistance to the capacitors will reduce
the effective charging efficiency. In the case of CBOT this
resistance can be kelvined out by a dedicated voltage
sense trace from the VMID pin to a point halfway between
the bottom plate of CTOP and the top plate of CBOT. In the
case of CTOP, however, it is even more critical to keep any
resistance in the connection to a minimum. Excessive
series resistance may cause the part to duty cycle in and
out of sleep or prematurely shut down the boost, due to
the voltage seen at the part being equal to VOUT + IOUT
ESR.LikewisetheCBOTsupercapacitorshouldbeprovided
with a low impedance contact to the ground plane with
an unbroken, low impedance, path back to the backside
of the LTC3625/LTC3625-1 package.
When laying out the printed circuit, the following check-
list should be used to ensure proper operation of the
LTC3625/LTC3625-1.
1. Are the bypass capacitors at VIN and VOUT as close as
possible to the LTC3625/LTC3625-1? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers. Minimizing inductance from these
capacitors to the LTC3625/LTC3625-1 is a top priority.
2. AretheCBOTbypasscapacitorandthepowerinductor(s)
closely connected? The (–) terminal of the CBOT bypass
capacitor returns current to the GND plane, and then
back to CIN.
3. Keep sensitive components away from the SW pins.
4. Keep the current carrying traces from VOUT to CTOP and
the inductors to CBOT to a minimum.
Typical applicaTions
450mA Charge Current 1-Inductor Application
VOUT
VMID
SW2
SW1
R3
71.5k
LTC3625-1
PROG
GND
*25mA MINIMUM LOAD REQUIRED ON VIN
C2 ≥ 0.1F
C3 ≥ 0.1F
VOUT
4.0V/4.5V
3625 TA03
C1
10F
R1
287k
R2
100k
VIN*
2.7V TO 5.5V
VIN
EN
CTL
VSEL
PGOOD
PFO
PFI
L1 3.3H
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC3625EDE#TRPBF | POWER SUPPLY SUPPORT CKT, PDSO12 |
| LTC3625IDE-1#TRPBF | POWER SUPPLY SUPPORT CKT, PDSO12 |
| LTC3632EMS8E#TRPBF | 0.06 A SWITCHING REGULATOR, PDSO8 |
| LTC3632IDD#TRPBF | 0.06 A SWITCHING REGULATOR, PDSO8 |
| LTC3632EDD#PBF | 0.06 A SWITCHING REGULATOR, PDSO8 |
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