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參數(shù)資料
| 型號(hào)： | LTC3625IDE-1#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | POWER SUPPLY SUPPORT CKT, PDSO12 |
| 封裝： | 3 X 4 MM, 0.75 MM HEIGHT, LEAD FREE, PLASTIC, MO-229WGED, DFN-12 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 262K |
| 代理商： | LTC3625IDE-1#PBF |
LTC3625/LTC3625-1
3625f
Typical perForMance characTerisTics
TA = 25°C, L1 = 3.3H, L2 = 3.3H, CIN = 10F, CTOP = CBOT, LTC3625 unless otherwise specified.
SW1 (Pin 1): Switch Pin for the Buck Regulator. External
inductor connects between SW1 pin and VMID.
VIN (Pin 2): Input Voltage Pin. Bypass to GND with a 10F
or larger ceramic capacitor.
CTL (Pin 3): Logic Input. CTL sets the charge mode of the
LTC3625/LTC3625-1.AlogichighatCTLprogramsthepart
to operate with a single inductor; a logic low programs
the part to operate with two inductors. In the 2-inductor
application the capacitor stack will charge approximately
twice as quickly. CTL is a high impedance input and must
be tied to either VIN or GND. Do not float.
VSEL (Pin 4): Logic Input. VSEL selects the output volt-
age of the LTC3625/LTC3625-1. A logic low at VSEL sets
the per-cell maximum voltage to 2.45V/2.05V (VOUT =
4.8V/4.0V); a logic high sets the per-cell maximum volt-
age to 2.70V/2.30V (VOUT = 5.3V/4.5V). When the part is
enabled, VSEL has a 4.5MΩ internal pull-down resistor; if
EN is low, then VSEL is a high impedance input pin.
EN (Pin 5): Logic Input. Enables the LTC3625/LTC3625-1.
Active high. Has a 4.5MΩ internal pull-down resistor.
Charge Profile Into Matched
SuperCaps
Charge Profile with CBOT > CTOP
Charge Profile with CTOP > CBOT
pin FuncTions
PROG (Pin 6): Charge Current Program Pin. Connecting a
resistor from PROG to ground programs the buck output
current. This pin servos to 1.2V.
PFI (Pin 7): Input to the Power Fail Comparator. This pin
connects to an external resistor divider between VIN and
GND. If this functionality is not desired, PFI should be
tied to VIN.
PFO(Pin8):Open-DrainOutputofthePower-FailCompara-
tor. The part pulls this pin low if VIN is less than a value
programmed by an external divider. This pin is active low
in shutdown mode. If this functionality is not desired PFO
should be left unconnected.
PGOOD (Pin 9): Logic Output. This is an open-drain
output which indicates that VOUT has settled to its final
value. Upon start-up, this pin remains low until the output
voltage, VOUT, is within 92.5% (typical) of its final value.
Once VOUT is valid, PGOOD becomes high impedance. If
VOUT falls to 89.5% (typical) of its correct regulation level,
PGOOD is pulled low. PGOOD may be pulled up through
an external resistor to an appropriate reference level. This
pin is active low in shutdown mode.
TIME (SECONDS)
0
SINGLE
INDUCTOR
VOLTAGE
(V)
DUAL
INDUCTOR
VOLTAGE
(V)
0
2
4
120
3625 G16
6
4
20
40
60
80 100
140
2
0
6
VOUT
VMID
VIN = 3.6V, VSEL = 3.6V
RPROG = 143k
CTOP = CBOT = 10F
VOUT
SINGLE INDUCTOR APPLICATION
DUAL INDUCTOR APPLICATION
TIME (SECONDS)
0
SINGLE
INDUCTOR
VOLTAGE
(V)
DUAL
INDUCTOR
VOLTAGE
(V)
0
2
4
200
3625 G17
6
4
50
100
150
250
2
0
6
VOUT
VMID
VIN = 3.6V, VSEL = 3.6V
RPROG = 143k
CTOP = 10F, CBOT = 50F
VOUT
SINGLE INDUCTOR APPLICATION
DUAL INDUCTOR APPLICATION
TIME (SECONDS)
0
SINGLE
INDUCTOR
VOLTAGE
(V)
DUAL
INDUCTOR
VOLTAGE
(V)
0
2
4
300
3625 G18
6
4
50
100 150 200 250
350
2
0
6
VOUT
VMID
VOUT
SINGLE INDUCTOR APPLICATION
DUAL INDUCTOR APPLICATION
VIN = 3.6V, VSEL = 3.6V
RPROG = 143k
CTOP = 50F, CBOT = 10F
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