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參數(shù)資料
| 型號： | LTC3588IDD-1#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, PDSO10 |
| 封裝： | 3 X 3 MM, LEAD FREE, PLASTIC, MO-229WEED-2, DFN-10 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 391K |
| 代理商： | LTC3588IDD-1#TRPBF |
LTC3588-1
8
35881fa
The LTC3588-1 is an ultralow quiescent current power
supply designed specically for energy harvesting and/or
low current step-down applications. The part is designed to
interface directly to a piezoelectric or alternative A/C power
source, rectify a voltage waveform and store harvested
energy on an external capacitor, bleed off any excess power
via an internal shunt regulator, and maintain a regulated
output voltage by means of a nanopower high efciency
synchronous buck regulator.
Internal Bridge Rectier
The LTC3588-1 has an internal full-wave bridge rectier
accessible via the differential PZ1 and PZ2 inputs that
recties AC inputs such as those from a piezoelectric
element. The rectied output is stored on a capacitor at
the VIN pin and can be used as an energy reservoir for the
buck converter. The low-loss bridge rectier has a total
drop of about 400mV with typical piezo generated currents
(~10μA). The bridge is capable of carrying up to 50mA.
One side of the bridge can be operated as a single-ended
DC input. PZ1 and PZ2 should never be shorted together
when the bridge is in use.
Undervoltage Lockout (UVLO)
When the voltage on VIN rises above the UVLO rising
threshold the buck converter is enabled and charge is
transferred from the input capacitor to the output capacitor.
A wide (~1V) UVLO hysteresis window is employed
with a lower threshold approximately 300mV above the
selected regulated output voltage to prevent short cycling
during buck power-up. When the input capacitor voltage
is depleted below the UVLO falling threshold the buck
converter is disabled. Extremely low quiescent current
(450nA typical) in UVLO allows energy to accumulate on
the input capacitor in situations where energy must be
harvested from low power sources.
Internal Rail Generation
Two internal rails, CAP and VIN2,aregeneratedfromVIN and
are used to drive the high side PMOS and low side NMOS
of the buck converter, respectively. Additionally the VIN2
rail serves as logic high for output voltage select bits D0
and D1. The VIN2 rail is regulated at 4.8V above GND while
the CAP rail is regulated at 4.8V below VIN. These are not
intended to be used as external rails. Bypass capacitors
are connected to the CAP and VIN2 pins to serve as energy
reservoirs for driving the buck switches. When VIN is below
4.8V, VIN2 is equal to VIN and CAP is held at GND. Figure 1
shows the ideal VIN, VIN2 and CAP relationship.
Figure 1. Ideal VIN, VIN2 and CAP Relationship
VIN (V)
0
VOL
TAGE
(V)
18
12
14
16
10
2
4
8
6
0
10
5
35881 F01
15
VIN
VIN2
CAP
OPERATION
Buck Operation
The buck regulator uses a hysteretic voltage algorithm
to control the output through internal feedback from the
VOUT sense pin. The buck converter charges an output
capacitor through an inductor to a value slightly higher than
the regulation point. It does this by ramping the inductor
current up to 260mA through an internal PMOS switch
and then ramping it down to 0mA through an internal
NMOS switch. This efciently delivers energy to the output
capacitor. The ramp rate is determined by VIN, VOUT, and
the inductor value. If the input voltage falls below the
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