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參數(shù)資料
| 型號： | LTC3569IUD#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.5 A SWITCHING REGULATOR, 3000 kHz SWITCHING FREQ-MAX, PQCC20 |
| 封裝： | 3 X 3 MM, LEAD FREE, PLASTIC, QFN-20 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大小： | 468K |
| 代理商： | LTC3569IUD#PBF |
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LTC3569
14
3569fd
APPLICATIONS INFORMATION
Operating Frequency
Selection of the operating frequency is a trade-off between
efficiency and component size. High frequency operation
allowsforsmallerinductorandcapacitorvalues.Operation
at lower frequencies improves the efficiency by reducing
internal gate charge losses but requires larger inductance
values and/or capacitance to maintain low output ripple
voltage.
Theoperatingfrequency,fCLK,oftheLTC3569isdetermined
by an external resistor that is connected between the RT
pin and ground. The value of the resistor sets the ramp
current that charges and discharges an internal timing
capacitor within the oscillator. The relationship between
oscillator frequency and RT is calculated by the following
equation:
RT = (5.1855 1011) (fCLK)–1.027
Or may be selected following the graph in Figure 4.
Minimum On-Time And Duty-Cycle
The maximum usable operating frequency is limited by
the minimum on-time and the required duty cycle. In buck
regulators, the duty cycle (DC) is the ratio of output to
input voltage: DC = VOUT/VIN = tON/(tOFF + tON). At low duty
cycles, the SW node is high for a small fraction of the total
clock period. As this time period approaches the speed
of the gate drive circuits and the comparators internal to
the LTC3569, the dynamic loop response suffers. To avoid
minimum on-time issues it is recommended to adjust the
operating frequency down so as to keep the minimum
duty cycle pulse width above 80ns. Thus, the maximum
operating frequency should be selected such that the duty
cycle does not demand SW pulse widths below the mini-
mum on-time. The maximum clock frequency, fCLKMAX,
is selected from either the internal fixed frequency clock,
or a timing resistor at the RT pin, or synchronizing clock
applied to the MODE pin. The minimum on-time require-
ment is met by adhering to the following formula:
fCLKMAX = (VOUT/VIN(MAX))/tMIN-ON
For example, if VOUT is 0.8V and VIN ranges up to 5.5V,
the maximum clock frequency is limited to no more than
1.8MHz.
Mode Selection And Frequency Synchronization
The MODE pin is a multi-purpose pin which provides
mode selection and frequency synchronization. Connect-
ing this pin to SVIN enables Burst Mode operation, which
provides the best low current efficiency at the cost of a
higher output voltage ripple. When this pin is connected
to ground, pulse-skipping operation is selected which
provides the lowest output voltage and current ripple at
the cost of low current efficiency.
Synchronize the LTC3569 to an external clock signal by
tying a clock source to the MODE pin. Select the RT pin
resistance so that the internal oscillator frequency is set
to 20% lower than the applied external clock frequency to
ensure adequate slope compensation, since slope com-
pensation is derived from the internal oscillator. During
synchronization, the mode is set to pulse skipping.
TheexternalclocksourceappliedtotheMODEpinrequires
minimum low and high pulse widths of about 100ns.
Figure 4. fCLK vs RT
The minimum frequency is limited by leakage and noise
coupling due to the large resistance of RT.
If the RT pin is tied to SVIN the oscillation frequency is
fixed at 2.25MHz.
Keep excess capacitance and noise (e.g., from the SW
pins) away from the RT pin. It is recommended to remove
the GND plane beneath the RT pin trace, and to route the
RT pin PCB trace away from the SW pins.
RT (M)
0
f CLK
(MHz)
4.1
3.6
2.6
1.1
1.6
3.1
2.1
0.6
0.1
0.4
0.2
3569 F04
0.6
0.3
0.1
0.5
VIN = 3.6V
TA = 25°C
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