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參數(shù)資料
| 型號： | LTC3542IS6#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, 2700 kHz SWITCHING FREQ-MAX, PDSO6 |
| 封裝： | LEAD FREE, PLASTIC, MO-193, TSOT-23, 6 PIN |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 211K |
| 代理商： | LTC3542IS6#PBF |
LTC3542
3
3542fa
TYPICAL PERFORMANCE CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. No pin should exceed 6V.
Note 2: The LTC3542 is guaranteed to meet performance specications
from 0°C to 85°C. Specications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3542I is guaranteed over the full
–40°C to 125°C operating temperature range.
Note 3: Failure to solder the Exposed Pad of the package to the PC board
will result in a thermal resistance much higher than 102°C/W.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IS
Input DC Supply Current (Note 5)
Active Mode
Sleep Mode
Shutdown
VFB = 0.5V
VFB = 0.7V, MODE = 0V
RUN = 0V
26
0.1
500
35
1
μA
fOSC
Oscillator Frequency
VFB = 0.6V
●
1.8
2.25
2.7
MHz
fSYNC
Synchronous Frequency
VFB = 0.6V
1
3
MHz
ILIM
Peak Switch Current
VIN = 3V, VFB = 0.5V, Duty Cycle < 35%
650
1000
mA
RDS(ON)
P-Channel On Resistance (Note 6)
N-Channel On Resistance (Note 6)
ISW = 100mA
ISW = –100mA
0.5
0.35
0.65
0.55
Ω
ISW(LKG)
Switch Leakage Current
VIN = 5V, VRUN = 0V, VSW = 0V or 5V
±0.01
±1
μA
VUVLO
Undervoltage Lockout Threshold
VIN Rising
VIN Falling
1.8
2.0
1.9
2.3
V
VRUN
RUN Threshold
●
0.3
1.5
V
IRUN
RUN Leakage Current
●
±0.01
±1
μA
VMODE/SYNC
MODE/SYNC Threshold
●
0.3
1.2
V
IMODE/SYNC
MODE/SYNC Leakage Current
●
±0.01
±1
μA
Note 4: The converter is tested in a proprietary test mode that connects
the output of the error amplier to the SW pin, which is connected to an
external servo loop.
Note 5: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 6: The DFN switch on resistance is guaranteed by correlation to wafer
level measurements.
Note 7: TJ is calculated from the ambient temperature TA and power
dissipation PD according to the following formula:
TJ = TA + (PD) (θJA).
Burst Mode Operation
Pulse Skip Mode Operation
Start-Up from Shutdown
SW
2V/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 25mA
FIGURE 3a CIRCUIT
2
μs/DIV
3542 G01
VOUT
50mV/DIV
AC COUPLED
IL
100mA/DIV
SW
2V/DIV
IL
100mA/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 25mA
FIGURE 3a CIRCUIT
400ns/DIV
3542 G02
VOUT
50mV/DIV
AC COUPLED
RUN
2V/DIV
IL
100mA/DIV
VIN = 3.6V
VOUT = 1.8V
ILOAD = 0A
FIGURE 3a CIRCUIT
400
μs/DIV
3542 G03
VOUT
1V/DIV
TA = 25°C unless otherwise specied.
ELECTRICAL CHARACTERISTICS The ● denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. VIN = 3.6V unless otherwise noted.
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