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參數(shù)資料
| 型號： | LTC2442 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er |
| 中文描述： | 24位高速4通道Δ-ΣADC的呃綜合擴(kuò)增 |
| 文件頁數(shù)： | 8/32頁 |
| 文件大小： | 392K |
| 代理商： | LTC2442 |
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LTC2442
8
2442f
MUXOUTA (Pin 27):
Multiplexer Output. Must tie to +INA
amplifier input (Pin 25).
COM (Pin 28):
The common negative input (SEL
–
) for all
single ended multiplexer configurations. The voltage on
CH0-CH3 and COM pins can have any value between GND
–0.3V to V
CC
+0.3V. Within these limits, the two selected
inputs (SEL
+
and SEL
–
) provide a bipolar input range (V
IN
= SEL
+
– SEL
–
) from –0.5 V
REF
to 0.5 V
REF
. Outside
this input range, the converter produces unique over-range
and under-range output codes.
V
CC
(Pin 29):
Positive Supply Voltage. Bypass to GND with
a 10μF tantalum capacitor in parallel with a 0.1μF ceramic
capacitor as close to the part as possible.
REF
+
(Pin 30), REF
–
(Pin 31):
Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
maintained more positive than the negative reference input,
REF
–
, by at least 0.1V. Bypass to GND with 0.1μF Ceramic
capacitor as close to the part as possible.
SDI (Pin 33):
Serial Data Input. This pin is used to select
the speed, 1X or 2X mode, resolution and input channel
for the next conversion cycle. At initial power up, the de-
fault mode of operation is CH0-CH1, OSR of 256 and 1X
mode. The serial data input contains an enable bit which
determines if a new channel/speed is selected. If this bit is
low the following conversion remains at the same speed
and selected channel. The serial data input is applied to
the device under control of the serial clock (SCK) during
the data output cycle. The first conversion following a new
channel/speed is valid.
F
0
(Pin 34):
Frequency Control Pin. Digital input that con-
trols the internal conversion clock. When F
0
is connected
to V
CC
or GND, the converter uses its internal oscillator
running at 9MHz. The conversion rate is determined by the
selected OSR such that t
CONV
(ms) = 40 OSR + 170/f
OSC
(kHz). The first digital filter null is located at 8/t
CONV
, 7kHz
at OSR = 256 and 55Hz (Simultaneous 50Hz/60Hz at OSR
= 32768. This pin may be driven with a maximum external
clock of 10.24MHz resulting in a maximum 8kHz output
rate (OSR = 64, 2X mode).
CS (Pin 35):
Active Low Chip Select. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the sleep mode and remains in this state as long as CS is
HIGH. A LOW-to-HIGH transition on CS during the Data
Output aborts the data transfer and starts a new conver-
sion.
SDO (Pin 36):
Three-State Digital Output. During the data
output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
CC
) the SDO pin is in
a high impedance state. During the conversion and sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
This signal is HIGH while the conversion is in progress
and goes LOW once the conversion is complete.
PU
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|---|---|
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| LTC2442CG#TRPBF | 功能描述:IC ADC 24BIT 250MSPS 36-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
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