參數(shù)資料
型號(hào)： LTC2442
廠商： Linear Technology Corporation
英文描述： 24-Bit High Speed 4-Channel Delta-Sigma ADC with Integrated Amplifi er
中文描述： 24位高速4通道Δ-ΣADC的呃綜合擴(kuò)增
文件頁(yè)數(shù)： 11/32頁(yè)
文件大?。?/td> 392K
代理商： LTC2442
LTC2442
11
2442f
Reference Voltage Range
The LTC2442
ΔΣ
converter accepts a truly differential
external reference voltage. The absolute/common mode
voltage specification for the REF
+
and REF
–
pins covers
the entire range from GND to V
CC
. For correct converter
operation, the REF
+
pin must always be more positive
than the REF
–
pin.
The LTC2442 can accept a differential reference voltage
from 0.1V to V
CC
. The converter output noise is determined
by the thermal noise of the front-end circuits, and as such,
its value in microvolts is nearly constant with reference
voltage. A decrease in reference voltage will not signifi-
cantly improve the converter’s effective resolution. On the
other hand, a reduced reference voltage will improve the
converter’s overall INL performance.
Input Voltage Range
The analog input is truly differential with an absolute/com-
mon mode range for the CH0-CH3 and COM input pins
extending from GND – 0.3V to V
CC
+ 0.3V. Outside these
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2442 converts the bipolar differential
input signal, V
IN
= SEL
+
– SEL
–
, from –FS = –0.5 V
REF
to +FS = 0.5 V
REF
where V
REF
= REF
+
– REF
–
. Outside
this range, the converter indicates the overrange or the
underrange condition using distinct output codes.
Output Data Format
The LTC2442 serial output data stream is 32 bits long.
The first three bits represent status information indicating
the sign and conversion state. The next 24 bits are the
conversion result, MSB first. The remaining five bits are
sub LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution. In the
case of ultrahigh resolution modes, more than 24 effective
bits of performance are possible (see Table 4). Under these
conditions, sub LSBs are included in the conversion result
and represent useful information beyond the 24-bit level.
The third and fourth bit together are also used to indicate
an underrange condition (the differential input voltage
is below –FS) or an overrange condition (the differential
input voltage is above +FS).
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0,
this bit is LOW.
Bit 28 (fourth output bit) is the most significant bit (MSB) of
the result. This bit in conjunction with Bit 29 also provides
the underrange or overrange indication. If both Bit 29 and
Bit 28 are HIGH, the differential input voltage is above +FS.
If both Bit 29 and Bit 28 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2442 Status Bits
Input Range
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
V
IN
≥ 0.5 V
REF
0V ≤ V
IN
< 0.5 V
REF
–0.5 V
REF
≤ V
IN
< 0V
V
IN
< –0.5 V
REF
Bits 28-5 are the 24-bit conversion result MSB first.
Bit 5 is the least significant bit (LSB).
Bits 4-0 are sub LSBs below the 24-bit level. Bits 4-0
may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must first be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
microcontroller. Bit 31 (EOC) can be captured on the first
rising edge of SCK. Bit 30 is shifted out of the device on
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
APPLICATIU
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U
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