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參數(shù)資料
| 型號： | LTC2428 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit 2.5-V to 3.3-V/3.3-V To 5-V Level Shifting Transceiver With 3-State Outputs 48-TSSOP -40 to 85 |
| 中文描述： | 4-/8-Channel 20位ADC的無延遲uPower |
| 文件頁數(shù)： | 12/28頁 |
| 文件大小： | 317K |
| 代理商： | LTC2428 |
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12
LTC2424/LTC2428
APPLICATIO
S I
N
FOR
ATIO
U
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2424/
LTC2428 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the F
O
pin and turns off the internal
oscillator. The frequency f
EOSC
of the external signal must
be at least 2560Hz (1Hz notch frequency) to be detected.
The external clock signal duty cycle is not significant as
long as the minimum and maximum specifications for the
high and low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2424/LTC2428 provide better
than 110dB normal mode rejection in a frequency range
f
EOSC
/2560
±
4% and its harmonics. The normal mode
rejection as a function of the input frequency deviation
from f
EOSC
/2560 is shown in Figure 5.
Whenever an external clock is not present at the F
O
pin the
converter automatically activates its internal oscillator
and enters the Internal Conversion Clock mode. The
LTC2424/LTC2428 operation will not be disturbed if the
change of conversion clock source occurs during the
sleep state or during the data output state while the
W
U
Figure 5. LTC2424/LTC2428 Normal Mode Rejection When
Using an External Oscillator of Frequency f
EOSC
converter uses an external serial clock. If the change
occurs during the conversion state, the result of the
conversion in progress may be outside specifications but
the following conversions will not be affected. If the
change occurs during the data output state and the
converter is in the Internal SCK mode, the serial clock duty
cycle may be affected but the serial data stream will
remain valid.
Table 4 summarizes the duration of each state as a
function of F
O
.
INPUT FREQUENCY DEVIATION FROM NOTCH FREQUENCY (%)
–12
–8
–4
0
4
8
12
R
24248 F05
–60
–70
–80
–90
–100
–110
–120
–130
–140
Table 4. LTC2424/LTC2428 State Duration
State
Operating Mode
CONVERT
Internal Oscillator
Duration
133ms
160ms
20480/f
EOSC
(In Seconds)
F
O
= LOW (60Hz Rejection)
F
O
= HIGH (50Hz Rejection)
F
O
= External Oscillator
with Frequency f
EOSC
kHz
(f
EOSC
/2560 Rejection)
External Oscillator
SLEEP
DATA OUTPUT
As Long As CSADC = HIGH Until CSADC = 0 and SCK
As Long As CSADC = LOW But Not Longer Than 1.67ms
(32 SCK cycles)
As Long As CSADC = LOW But Not Longer Than 256/f
EOSC
ms
(32 SCK cycles)
As Long As CSADC = LOW But Not Longer Than 32/f
SCK
ms
(32 SCK cycles)
1
Internal Serial Clock
F
O
= LOW/HIGH
(Internal Oscillator)
F
O
= External Oscillator with
Frequency f
EOSC
kHz
External Serial Clock with
Frequency f
SCK
kHz
MAXIMUM OUTPUT
WORD RATE (OWR)
OWR
t
t
inHz
CONVERT
DATAOUTPUT
=
+
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