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參數(shù)資料
| 型號： | LTC2362CTS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 500KSPS TSOT23-8 |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.2mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應商設備封裝： | TSOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 配用： | DC1190A-C-ND - BOARD SAR ADC LTC2362 |
LTC2360/LTC2361/LTC2362
9
236012fa
PIN FUNCTIONS
S6 Package
VDD (Pin 1): Positive Supply. The VDD range is 2.35V to
3.6V. VDD also denes the input span of the ADC, 0V to
VDD. Bypass to GND and to a solid ground plane with a
2.2μF ceramic capacitor (or 2.2μF tantalum in parallel
with 0.1μF ceramic).
GND (Pin 2): Ground. The GND pin must be tied directly
to a solid ground plane.
AIN (Pin 3): Analog Input. AIN is a single-ended input with
respect to GND with a range from 0V to VDD.
SCK (Pin 4): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions on
the falling edge of SCK.
SDO (Pin 5): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB rst. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
CONV (Pin 6): Convert Input. This active high signal starts
a conversion on the rising edge. The device automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
TS8 Package
VDD (Pin 1): Positive Supply. The VDD range is 2.35V to
3.6V. Bypass to GND and to a solid ground plane with a
2.2μF ceramic capacitor (or 2.2μF tantalum in parallel
with 0.1μF ceramic).
VREF (Pin 2): Reference Input. VREF denes the input
span of the ADC, 0V to VREF. The VREF range is 1.4V to
VDD. Bypass to GND and to a solid ground plane with a
2.2μF ceramic capacitor (or 2.2μF tantalum in parallel
with 0.1μF ceramic).
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
AIN (Pin 4): Analog Input. AIN is a single-ended input with
respect to GND with a range from 0V to VREF.
OVDD (Pin 5): Output Driver Supply for SDO. The OVDD
range is 1V to VDD. Bypass to GND and to a solid ground
plane with a 2.2μF ceramic capacitor (or 2.2μF tantalum in
parallel with 0.1μF ceramic). OVDD can be driven separately
from VDD and OVDD can be higher than VDD.
SDO (Pin 6): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB rst. The data stream consists of 12 bits
of conversion data followed by trailing zeros.
SCK (Pin 7): Shift Clock Input. The SCK serial clock syn-
chronizes the serial data transfer. SDO data transitions on
the falling edge of SCK.
CONV (Pin 8): Convert Input. This active high signal starts
a conversion on the rising edge. The device automatically
powers down after conversion. A logic low on this input
enables the SDO pin, allowing the data to be shifted out.
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