參數(shù)資料
型號: LTC2299CUP#TRPBF
廠商: Linear Technology
文件頁數(shù): 1/24頁
文件大?。?/td> 0K
描述: IC ADC DUAL 14BIT 80MSPS 64QFN
標準包裝: 2,000
位數(shù): 14
采樣率(每秒): 80M
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 2
功率耗散(最大): 516mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 64-WFQFN 裸露焊盤
供應商設備封裝: 64-QFN(9x9)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 2 個單端,雙極; 2 個差分, 雙極
LTC2299
1
2299fa
INPUT FREQUENCY (MHz)
0
65
SNR
(dBFS)
66
68
69
70
75
72
50
100
2299 TA02
67
73
74
71
150
200
+
INPUT
S/H
ANALOG
INPUT A
ANALOG
INPUT B
CLK A
CLK B
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY CYCLE
CONTROL
OUTPUT
DRIVERS
OVDD
OGND
MUX
D13A
D0A
OVDD
OGND
2299 TA01
D13B
D0B
+
OUTPUT
DRIVERS
INPUT
S/H
14-BIT
PIPELINED
ADC CORE
CLOCK/DUTY CYCLE
CONTROL
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
Integrated Dual 14-Bit ADCs
Sample Rate: 80Msps
Single 3V Supply (2.7V to 3.4V)
Low Power: 444mW
73dB SNR at 70MHz Input
90dB SFDR at 70MHz Input
110dB Channel Isolation at 100MHz
Multiplexed or Separate Data Bus
Flexible Input: 1VP-P to 2VP-P Range
575MHz Full Power Bandwidth S/H
Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Pin Compatible Family
105Msps: LTC2282 (12-Bit), LTC2284 (14-Bit)
80Msps: LTC2294 (12-Bit), LTC2299 (14-Bit)
65Msps: LTC2293 (12-Bit), LTC2298 (14-Bit)
40Msps: LTC2292 (12-Bit), LTC2297 (14-Bit)
25Msps: LTC2291 (12-Bit), LTC2296 (14-Bit)
64-Pin (9mm
× 9mm) QFN Package
Dual 14-Bit, 80Msps
Low Power 3V ADC
The LTC
2299 is a 14-bit 80Msps, low power dual 3V
A/D converter designed for digitizing high frequency, wide
dynamic range signals. The LTC2299 is perfect for
demanding imaging and communications applications
with AC performance that includes 73dB SNR and 90dB
SFDR for signals well beyond the Nyquist frequency.
DC specs include
±1.2LSB INL (typ), ±0.5LSB DNL (typ)
and
±5LSB INL, ±1LSB DNL over temperature. The transi-
tion noise is a low 1.2LSBRMS.
A single 3V supply allows low power operation. A separate
output supply allows the outputs to drive 0.5V to 3.6V
logic. An optional multiplexer allows both channels to
share a digital output bus.
A single-ended CLK input controls converter operation. An
optional clock duty cycle stabilizer allows high perfor-
mance at full speed for a wide range of clock duty cycles.
SNR vs Input Frequency,
–1dB, 2V Range
Wireless and Wired Broadband Communication
Imaging Systems
Spectral Analysis
Portable Instrumentation
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