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參數資料
| 型號： | LTC2240IUP-12#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 11/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 170MSPS 64-QFN |
| 標準包裝： | 40 |
| 位數： | 12 |
| 采樣率（每秒）： | 170M |
| 數據接口： | 并聯 |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 638mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 管件 |
| 輸入數目和類型： | 1 個差分，雙極 |
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LTC2240-12
19
224012fd
APPLICATIONS INFORMATION
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC2240-12 is 210Msps.
For the ADC to operate properly, the encode signal should
have a 50% (±5%) duty cycle. Each half cycle must have at
least 2.79ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise
50% duty cycle is easy with differential sinusoidal drive
using a transformer or using symmetric differential logic
such as PECL or LVDS.
An optional clock duty cycle stabilizer circuit can be used if
the input clock has a non 50% duty cycle. This circuit uses
the rising edge of the ENC+ pin to sample the analog input.
The falling edge of ENC+ is ignored and the internal falling
edge is generated by a phase-locked loop. The input clock
duty cycle can vary from 40% to 60% and the clock duty
cycle stabilizer will maintain a constant 50% internal duty
cycle. If the clock is turned off for a long period of time,
the duty cycle stabilizer circuit will require one hundred
clock cycles for the PLL to lock onto the input clock. To
use the clock duty cycle stabilizer, the MODE pin should be
connected to 1/3VDD or 2/3VDD using external resistors.
The lower limit of the LTC2240-12 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specied minimum operating frequency
for the LTC2240-12 is 1Msps.
Figure 11. Transformer Driven ENC+/ENC–
Figure 12a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 12b. ENC Drive Using LVDS
VDD
LTC2240-12
224012 F11
VDD
ENC–
ENC+
1.5V BIAS
0.1μF
T1
MA/COM
ETC1-1-13
CLOCK
INPUT
100Ω
8.2pF
0.1μF
50Ω
50Ω
4.8k
TO INTERNAL
ADC CIRCUITS
224012 F12a
ENC–
1.5V
VTHRESHOLD = 1.5V
ENC+
0.1μF
LTC2240-12
224012 F12b
ENC–
ENC+
LVDS
CLOCK
100Ω
0.1μF
LTC2240-12
0.1μF
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LTC2240IUP-12-TR | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 170Msps ADC |
| LTC2240IUP-12-TRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 170Msps ADC |
| LTC2240UP-10 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:10-Bit, 170Msps ADC |
| LTC2240UP-12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:12-Bit, 170Msps ADC |
| LTC2241-10 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit 250Msps/ 210Msps/170Msps ADCs |
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