參數(shù)資料
型號(hào)： LTC2208UP-14
廠商： Linear Technology Corporation
英文描述： 14-Bit, 130Msps ADC
中文描述： 14位，130Msps ADC
文件頁數(shù)： 21/28頁
文件大小： 1056K
代理商： LTC2208UP-14
LTC2208-14
21
220814f
The internal programmable gain amplifier provides the
internal reference voltage for the ADC. This amplifier has
very stringent settling requirements and is not accessible
for external use.
The SENSE pin can be driven ±5% around the nominal 2.5V
or 1.25V external reference inputs. This adjustment range
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the
SENSE pin should be tied to V
DD
as close to the converter
as possible. If the sense pin is driven externally it should
be bypassed to ground as close to the device as possible
with 1μF ceramic capacitor.
Figure 7. A 2.25V Range ADC with an External 2.5V Reference
APPLICATIU
W
U
U
In applications where jitter is critical (high input frequen-
cies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using trans-
former coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a fixed frequency sinusoidal
signal, filter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to 3V. Each input may be driven from ground to V
DD
for
single-ended drive.
PGA Pin
The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.25V
P-P
; PGA
= 1 selects an input range of 1.5V
P-P
. The 2.25V input range
has the best SNR; however, the distortion will be higher for
input frequencies above 100MHz. For applications with high
input frequencies, the low input range will have improved
distortion; however, the SNR will be approximately 1.8dB
worse. See the typical performance curves section.
Driving the Encode Inputs
The noise performance of the LTC2208-14 can depend on
the encode signal quality as much as on the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
Figure 8a. Equivalent Encode Input Circuit
Figure 8b. Transformer Driven Encode
V
CM
SENSE
1.25V
3.3V
1
μ
F
2.2
μ
F
2.2
μ
F
220814 F07
LTC2208-14
LT1461-2.5
2
6
4
V
DD
V
DD
LTC2208-14
220814 F08a
V
DD
ENC–
ENC
+
1.6V
1.6V
6k
6k
TO INTERNAL
ADC CLOCK
DRIVERS
50
100
8.2pF
0.1
μ
F
0.1
μ
F
0.1
μ
F
T1
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50
LTC2208-14
220814 F08b
ENC–
ENC
+
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