參數(shù)資料
型號(hào)： LTC2207CUK-14
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 14-Bit, 105Msps/80Msps ADCs
中文描述： 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝： 7 X 7 MM, PLASTIC, MO-220WKKD-2, QFN-48
文件頁數(shù)： 14/32頁
文件大?。?/td> 1298K
代理商： LTC2207CUK-14
LTC2207-14/LTC2206-14
14
220714614fa
SENSE (Pin 1):
Reference Mode Select and External
Reference Input. Tie SENSE to V
DD
to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
V
CM
(Pin 2):
1.25V Output. Optimum voltage for input com-
mon mode. Must be bypassed to ground with a minimum
of 2.2μF. Ceramic chip capacitors are recommended.
V
DD
(Pins 3, 4, 12, 13, 14):
3.3V Analog Supply Pin.
Bypass to GND with 0.1μF ceramic chip capacitors.
GND (Pins 5, 8, 11, 15, 48):
ADC Power Ground.
A
IN+
(Pin 6):
Positive Differential Analog Input.
A
IN–
(Pin 7):
Negative Differential Analog Input.
ENC
+
(Pin 9):
Positive Differential Encode Input. The
sampled analog input is held on the rising edge of ENC
+
.
Internally biased to 1.6V through a 6.2k
Ω
resistor. Output
data can be latched on the rising edge of ENC
+
.
ENC
–
(Pin 10):
Negative Differential Encode Input. The
sampled analog input is held on the falling edge of ENC
–
.
Internally biased to 1.6V through a 6.2k
Ω
resistor. By-
pass to ground with a 0.1μF capacitor for a single-ended
Encode signal.
SHDN (Pin 16):
Power Shutdown Pin. SHDN = low results
in normal operation. SHDN = high results in powered
down analog circuitry and the digital outputs are placed
in a high impedance state.
DITH (Pin 17):
Internal Dither Enable Pin. DITH = low
disables internal dither. DITH = high enables internal
dither. Refer to Internal Dither section of this data sheet
for details on dither operation.
NC (Pins 18, 19):
No Connect.
D0-D13 (Pins 20-22, 26-28, 32-35 and 39-42):
Digital
Outputs. D13 is the MSB.
OGND (Pins 23, 31 and 38):
Output Driver Ground.
OV
DD
(Pins 24, 25, 36, 37):
Positive Supply for the Output
Drivers. Bypass to ground with 0.1μF capacitor.
CLKOUT
–
(Pin 29):
Data Valid Output. CLKOUT
–
will toggle
at the sample rate. Latch the data on the falling edge of
CLKOUT
–
.
CLKOUT
+
(Pin 30):
Inverted Data Valid Output. CLKOUT
+
will toggle at the sample rate. Latch the data on the rising
edge of CLKOUT
+
.
OF (Pin 43):
Over/Under Flow Digital Output. OF is high
when an over or under flow has occurred.
O
E (Pin 44):
Output Enable Pin. Low enables the digital
output drivers. High puts digital outputs in Hi-Z state.
MODE (Pin 45):
Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Connecting MODE to 0V selects
offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3V
DD
selects offset
binary output format and enables the clock duty cycle sta-
bilizer. Connecting MODE to 2/3V
DD
selects 2’s complement
output format and enables the clock duty cycle stabilizer.
Connecting MODE to V
DD
selects 2’s complement output
format and disables the clock duty cycle stabilizer.
RAND (Pin 46):
Digital Output Randomization Selection
Pin. RAND low results in normal operation. RAND high
selects D1-D13 to be EXCLUSIVE-ORed with D0 (the
LSB). The output can be decoded by again applying an
XOR operation between the LSB and all other bits. This
mode of operation reduces the effects of digital output
interference.
PGA (Pin 47):
Programmable Gain Amplifier Control Pin. Low
selects a front-end gain of 1, input range of 2.25V
P-P
. High
selects a front-end gain of 1.5, input range of 1.5V
P-P
.
GND (Exposed Pad, Pin 49):
ADC Power Ground. The ex-
posed pad on the bottom of the package must be soldered
to ground.
PIN FUNCTIONS
相關(guān)PDF資料
PDF描述
LTC2207IUK-14 14-Bit, 105Msps/80Msps ADCs
LTC2207UK-14 14-Bit, 105Msps/80Msps ADCs
LTC2206 16-Bit, 105Msps/80Msps ADCs
LTC2206CUK 16-Bit, 105Msps/80Msps ADCs
LTC2206IUK 16-Bit, 105Msps/80Msps ADCs
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