參數(shù)資料
型號(hào)： LTC2206IUK
廠商： LINEAR TECHNOLOGY CORP
元件分類(lèi)： ADC
英文描述： 16-Bit, 105Msps/80Msps ADCs
中文描述： 1-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝： 7 X 7 MM, PLASTIC, MO-220WKKD-2, QFN-48
文件頁(yè)數(shù)： 18/32頁(yè)
文件大小： 1489K
代理商： LTC2206IUK
LTC2207/LTC2206
18
22076fa
Figure 2. Equivalent Input Circuit
C
SAMPLE
V
DD
V
DD
LTC2207/LTC2206
A
IN+
22076 F02
C
SAMPLE
V
DD
A
IN
–
ENC
–
ENC
+
1.6V
6k
1.6V
6k
C
1.8pF
C
1.8pF
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2207/
LTC2206 CMOS differential sample and hold. The differ-
ential analog inputs are sampled directly onto sampling
capacitors (C
SAMPLE
) through NMOS transitors. The
capacitors shown attached to each input (C
PARASITIC
) are
the summation of all other capacitance associated with
each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors and they charge to, and track the differential
input voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions for high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specified performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The V
CM
output pin (Pin 2) is designed
to provide the common mode bias level. V
CM
can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The V
CM
pin must be bypassed to ground
close to the ADC with 2.2μF or greater.
Input Drive Impedence
As with all high performance, high speed ADCs the
dynamic performance of the LTC2207/LTC2206 can be
influenced by the input drive circuitry, particularly the
second and third harmonics. Source impedance and in-
put reactance can influence SFDR. At the falling edge of
ENC the sample-and-hold circuit will connect the 4.9pF
sampling capacitor to the input pin and start the sampling
period. The sampling period ends when ENC rises, hold-
ing the sampled input on the sampling capacitor. Ideally,
the input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F
ENCODE
); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recomended to have a source
impedence of 100
Ω
or less for each input. The source
impedence should be matched for the differential inputs.
Poor matching will result in higher even order harmonics,
especially the second.
APPLICATIONS INFORMATION
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