參數(shù)資料
型號： LTC2206CUK-14
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 14-Bit, 105Msps/80Msps ADCs
中文描述： 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝： 7 X 7 MM, PLASTIC, MO-220WKKD-2, QFN-48
文件頁數(shù)： 6/32頁
文件大?。?/td> 1298K
代理商： LTC2206CUK-14
LTC2207-14/LTC2206-14
6
220714614fa
t
H
t
D
t
C
t
L
N – 7
N – 6
N – 5
N – 4
N – 3
ANALOG
INPUT
ENC
–
ENC
+
CLKOUT
–
CLKOUT
+
D0-D13, OF
22076 TD01
t
AP
N + 1
N + 2
N + 4
N + 3
N
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to GND, with GND and OGND
shorted (unless otherwise noted).
Note 3:
When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
DD
without latchup.
Note 4:
V
DD
= 3.3V, f
SAMPLE
= 105MHz (LTC2207-14), 80MHz (LTC2206-
14) differential ENC
+
/ENC
–
= 2V
P-P
sine wave with 1.6V common mode,
input range = 2.25V
P-P
with differential drive (PGA = 0), unless otherwise
specified.
Note 5:
Integral nonlinearity is defined as the deviation of a code from a
“best fit straight line” to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 6:
Offset error is the offset voltage measured from –1/2LSB when the
output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111
in 2’s complement output mode.
Note 7:
Guaranteed by design, not subject to test.
Note 8:
The dynamic current of the switched capacitors analog inputs can
be large compared to the leakage current and will vary with the sample
rate.
Note 9:
Leakage current will have higher transient current at power up.
Keep drive resistance at or below 1Kohm.
range, otherwise specifications are at T
A
= 25°C. (Note 4)
The
●
denotes the specifications which apply over the full operating temperature
SYMBOL
f
S
t
L
PARAMETER
Sampling Frequency
ENC Low Time
CONDITIONS
MIN
1
5.94
4.06
5.94
4.06
LTC2206-14
TYP
MAX
80
500
500
500
500
MIN
1
4.52
3.10
4.52
3.10
LTC2207-14
TYP
MAX
105
500
500
500
500
UNITS
MHz
●
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
●
●
6.25
6.25
6.25
6.25
–0.7
4.762
4.762
4.762
4.762
–0.7
ns
ns
ns
ns
ns
t
H
ENC High Time
●
●
t
AP
Sample-and-Hold
Aperture Delay
ENC to DATA Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
DATA Access time
Bus Relinquish time
t
D
t
C
t
SKEW
t
OE
(Note 7)
(Note 7)
(t
C
-t
D
) (Note 7)
CL = 5pF (Note 7)
(Note 7)
●
1.3
1.3
–0.6
2.7
2.7
0
5
5
7
4
4
1.3
1.3
–0.6
2.7
2.7
0
5
5
7
4
4
ns
ns
ns
ns
ns
●
●
0.6
15
15
0.6
15
15
●
●
Pipeline
Latency
Cycles
TIMING DIAGRAM
TIMING CHARACTERISTICS
相關(guān)PDF資料
PDF描述
LTC2206IUK-14 14-Bit, 105Msps/80Msps ADCs
LTC2206UK-14 14-Bit, 105Msps/80Msps ADCs
LTC2207-14 14-Bit, 105Msps/80Msps ADCs
LTC2207CUK-14 14-Bit, 105Msps/80Msps ADCs
LTC2207IUK-14 14-Bit, 105Msps/80Msps ADCs
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