參數(shù)資料
型號(hào): LTC2206CUK-14
廠商: LINEAR TECHNOLOGY CORP
元件分類(lèi): ADC
英文描述: 14-Bit, 105Msps/80Msps ADCs
中文描述: 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
封裝: 7 X 7 MM, PLASTIC, MO-220WKKD-2, QFN-48
文件頁(yè)數(shù): 24/32頁(yè)
文件大?。?/td> 1298K
代理商: LTC2206CUK-14
LTC2207-14/LTC2206-14
24
220714614fa
APPLICATIONS INFORMATION
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
DD
, should be tied
to the same power supply as for the logic being driven.
For example, if the converter is driving a DSP powered
by a 1.8V supply, then OV
DD
should be tied to that same
1.8V supply. In CMOS mode OV
DD
can be powered with
any logic voltage up to the V
DD
of the ADC. OGND can be
powered with any voltage from ground up to 1V and must
be less than OV
DD
. The logic outputs will swing between
OGND and OV
DD
.
Internal Dither
The LTC2207-14/LTC2206-14 are 14-bit ADCs with a very
linear transfer function; however, at low input levels even
slight imperfections in the transfer function will result in
unwanted tones. Small errors in the transfer function are
usually a result of ADC element mismatches. An optional
internal dither mode can be enabled to randomize the input
location on the ADC transfer curve, resulting in improved
SFDR for low signal levels.
As shown in Figure 14, the output of the sample-and-hold
amplifier is summed with the output of a dither DAC. The
dither DAC is driven by a long sequence pseudo-random
Figure 13. Descrambling a Scrambled Digital Output
D1
D0
D2
D12
D13
LTC2207-14/
LTC2206-14
PC BOARD
FPGA
CLKOUT
OF
D13/D0
D12/D0
D2/D0
D1/D0
D0
2
相關(guān)PDF資料
PDF描述
LTC2206IUK-14 14-Bit, 105Msps/80Msps ADCs
LTC2206UK-14 14-Bit, 105Msps/80Msps ADCs
LTC2207-14 14-Bit, 105Msps/80Msps ADCs
LTC2207CUK-14 14-Bit, 105Msps/80Msps ADCs
LTC2207IUK-14 14-Bit, 105Msps/80Msps ADCs
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