- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385506 > LTC2205-14 (Linear Technology Corporation) 14-Bit, 65Msps ADC PDF資料下載
參數(shù)資料
| 型號(hào)： | LTC2205-14 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 14-Bit, 65Msps ADC |
| 中文描述： | 14位，型號(hào)各有不同的模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大小： | 1563K |
| 代理商： | LTC2205-14 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
LTC2205-14
16
220514fa
During the hold phase when ENC is high, the sampling
capacitors are disconnected from the input and the held
voltage is passed to the ADC core for processing. As ENC
transitions from high to low, the inputs are reconnected to
the sampling capacitors to acquire a new sample. Since
the sampling capacitors still hold the previous sample,
a charging glitch proportional to the change in voltage
between samples will be seen at this time. If the change
between the last sample and the new sample is small,
the charging glitch seen at the input will be small. If the
input change is large, such as the change seen with input
frequencies near Nyquist, then a larger charging glitch
will be seen.
Common Mode Bias
The ADC sample-and-hold circuit requires differential
drive to achieve specified performance. Each input should
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
for the 1.5V range (PGA = 1), around a common mode
voltage of 1.25V. The V
CM
output pin (Pin 2) is designed
to provide the common mode bias level. V
CM
can be tied
directly to the center tap of a transformer to set the DC
input level or as a reference level to an op amp differential
driver circuit. The V
CM
pin must be bypassed to ground
close to the ADC with 2.2μF or greater.
Input Drive Impedence
As with all high performance, high speed ADCs the dy-
namic performance of the LTC2205-14 can be influenced
by the input drive circuitry, particularly the second and
third harmonics. Source impedance and input reactance
can influence SFDR. At the falling edge of ENC the
sample-and-hold circuit will connect the 4.9pF sampling
capacitor to the input pin and start the sampling period.
The sampling period ends when ENC rises, holding the
sampled input on the sampling capacitor. Ideally, the
input circuitry should be fast enough to fully charge
the sampling capacitor during the sampling period
1/(2F
ENCODE
); however, this is not always possible and the
incomplete settling may degrade the SFDR. The sampling
glitch has been designed to be as linear as possible to
minimize the effects of incomplete settling.
For the best performance it is recomended to have a source
impedence of 100
or less for each input. The source
impedence should be matched for the differential inputs.
Poor matching will result in higher even order harmonics,
especially the second.
INPUT DRIVE CIRCUITS
Input Filtering
A first order RC lowpass filter at the input of the ADC can
serve two functions: limit the noise from input circuitry and
provide isolation from ADC S/H switching. The LTC2205-14
has a very broadband S/H circuit, DC to 700MHz; it can
be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC filter.
Figures 3, 4a and 4b show three examples of input RC
filtering at three ranges of input frequencies. In general
it is desirable to make the capacitors as large as can be
tolerated—this will help suppress random noise as well as
noise coupled from the digital circuitry. The LTC2205-14
does not require any input filter to achieve data sheet
specifications; however, no filtering will put more stringent
noise requirements on the input drive circuitry.
Transformer Coupled Circuits
Figure 3 shows the LTC2205-14 being driven by an RF
transformer with a center-tapped secondary. The secondary
center tap is DC biased with V
CM
, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used; however,
as the turns ratio increases so does the impedance seen by
the ADC. Source impedance greater than 50
can reduce
the input bandwidth and increase high frequency distor-
tion. A disadvantage of using a transformer is the loss of
low frequency response. Most small RF transformers have
poor performance at frequencies below 1MHz.
APPLICATIONS INFORMATION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2205CUK-14 | 14-Bit, 65Msps ADC |
| LTC2205IUK-14 | 14-Bit, 65Msps ADC |
| LTC2205UK-14 | 14-Bit, 65Msps ADC |
| LTC2206CUK-14 | 14-Bit, 105Msps/80Msps ADCs |
| LTC2206IUK-14 | 14-Bit, 105Msps/80Msps ADCs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2205CUK | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
| LTC2205CUK#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 65Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16-BIT 65MSPS 48-QFN 制造商:Linear Technology 功能描述:ADC 16BIT 65MSPS 48QFN 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS QFN-48 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 65MSPS, QFN-48; Resolution (Bits):16bit; Sampling Rate:65MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:185mA; Digital IC Case Style:QFN; No. of Pins:48 ;RoHS Compliant: Yes |
| LTC2205CUK#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 65Msps 16-bit Parallel 48-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16-BIT 65MSPS 48-QFN |
| LTC2205CUK-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 65Msps ADC |
| LTC2205CUK-14#PBF | 功能描述:IC ADC 14BIT 65MSPS 48-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。