- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385506 > LTC2205-14 (Linear Technology Corporation) 14-Bit, 65Msps ADC PDF資料下載
參數(shù)資料
| 型號： | LTC2205-14 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 14-Bit, 65Msps ADC |
| 中文描述： | 14位，型號各有不同的模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/28頁 |
| 文件大?。?/td> | 1563K |
| 代理商： | LTC2205-14 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁
LTC2205-14
15
220514fa
CONVERTER OPERATION
The LTC2205-14 is a CMOS pipelined multi-step converter
with a front-end PGA. As shown in Figure 1, the converter
has five pipelined ADC stages; a sampled analog input
will result in a digitized value seven cycles later (see the
Timing Diagram section). The analog input is differential for
improved common mode noise immunity and to maximize
the input range. Additionally, the differential input drive
will reduce even order harmonics of the sample and hold
circuit. The encode input is also differential for improved
common mode noise immunity.
The LTC2205-14 has two phases of operation, determined
by the state of the differential ENC
+
/ENC
–
input pins. For
brevity, the text will refer to ENC
+
greater than ENC
–
as
ENC high and ENC
+
less than ENC
–
as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and a residue amplifier. In opera-
tion, the ADC quantizes the input to the stage, and the
quantized value is subtracted from the input by the DAC
to produce a residue. The residue is amplified and output
by the residue amplifier. Successive stages operate out
of phase so that when odd stages are outputting their
residue, the even stages are acquiring that residue and
vice versa.
When ENC is low, the analog input is sampled differen-
tially directly onto the input sample-and-hold capacitors,
inside the “input S/H” shown in the block diagram. At the
instant that ENC transitions from low to high, the voltage
on the sample capacitors is held. While ENC is high, the
held input voltage is buffered by the S/H amplifier which
drives the first pipelined ADC stage. The first stage acquires
the output of the S/H amplifier during the high phase of
ENC. When ENC goes back low, the first stage produces
its residue which is acquired by the second stage. At
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage.
An identical process is repeated for the third and fourth
stages, resulting in a fourth stage residue that is sent to
the fifth stage for final evaluation.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
Sample/Hold Operation
Figure 2 shows an equivalent circuit for the LTC2205-14
CMOS differential sample and hold. The differential ana-
log inputs are sampled directly onto sampling capacitors
(C
SAMPLE
) through NMOS transitors. The capacitors shown
attached to each input (C
PARASITIC
) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
capacitors which charge to, and track the differential in-
put voltage. When ENC transitions from low to high, the
sampled input voltage is held on the sampling capacitors.
Figure 2. Equivalent Input Circuit
APPLICATIONS INFORMATION
C
SAMPLE
4.9pF
V
DD
V
DD
LTC2005-14
R
PARASITIC
3
R
ON
20
R
ON
20
R
PARASITIC
3
A
IN+
220514 F02
C
SAMPLE
V
DD
A
IN
–
ENC
–
ENC
+
1.6V
6k
1.6V
6k
C
1.8pF
C
1.8pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC2205CUK-14 | 14-Bit, 65Msps ADC |
| LTC2205IUK-14 | 14-Bit, 65Msps ADC |
| LTC2205UK-14 | 14-Bit, 65Msps ADC |
| LTC2206CUK-14 | 14-Bit, 105Msps/80Msps ADCs |
| LTC2206IUK-14 | 14-Bit, 105Msps/80Msps ADCs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2205CUK | 制造商:LINER 制造商全稱:Linear Technology 功能描述:16-Bit, 65Msps/40Msps |
| LTC2205CUK#PBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 65Msps 16-bit Parallel 48-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16-BIT 65MSPS 48-QFN 制造商:Linear Technology 功能描述:ADC 16BIT 65MSPS 48QFN 制造商:Linear Technology 功能描述:IC ADC 16BIT 65MSPS QFN-48 制造商:Linear Technology 功能描述:IC, ADC, 16BIT, 65MSPS, QFN-48; Resolution (Bits):16bit; Sampling Rate:65MSPS; Supply Voltage Type:Single; Supply Voltage Min:3.135V; Supply Voltage Max:3.465V; Supply Current:185mA; Digital IC Case Style:QFN; No. of Pins:48 ;RoHS Compliant: Yes |
| LTC2205CUK#TRPBF | 制造商:Linear Technology 功能描述:ADC Single Pipelined 65Msps 16-bit Parallel 48-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16-BIT 65MSPS 48-QFN |
| LTC2205CUK-14 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:14-Bit, 65Msps ADC |
| LTC2205CUK-14#PBF | 功能描述:IC ADC 14BIT 65MSPS 48-QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。