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參數(shù)資料
| 型號： | LTC1753 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 9-Bit D-Type Transparent Read-Back Latches With 3-State Outputs 24-PDIP 0 to 70 |
| 中文描述： | 5位可編程同步開關穩(wěn)壓器控制器的奔騰III處理器 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 269K |
| 代理商： | LTC1753 |
6
LTC1753
Expanded View of Overshoot
Illustrates 0% Duty Cycle
Operation, V
OUT
= 2.8V
Expanded View of Undershoot
Illustrates 100% Duty Cycle
Operation, V
OUT
= 2.8V
V
20mV/DIV
G1
10V/DIV
5
μ
s/DIV
1753 G18
V
20mV/DIV
G1
10V/DIV
5
μ
s/DIV
1753 G19
the SENSE pin, the initial output voltage can be raised
slightly. Since the internal divider has a nominal imped-
ance of 108k
, a 1100
series resistor will raise the
nominal output voltage by 1%. If an external resistor is
used, the value of the 1
μ
F capacitor on the SENSE pin must
be greatly reduced or loop phase margin will suffer. Set a
time constant for the RC combination of approximately
0.1
μ
s. So, for example, with a 1100
resistor, set
C = 90pF. Use a standard 100pF capacitor. In addition, LTC
recommends that the 1
μ
F capacitor be connected from the
top of the additional external resistor directly to SGND.
I
MAX
(Pin 7):
Current Limit Threshold. Current limit is set
by the voltage drop across an external resistor connected
between the drain of Q1 and I
MAX
. There is a 190
μ
A internal
pull-down at I
MAX
.
I
FB
(Pin 8):
Current Limit Sense Pin. Connect to the
switching node between the source of Q1 and the drain of
Q2. If I
FB
drops below I
MAX
when G1 is on, the LTC1753
will go into current limit. The current limit circuit can be
disabled by floating I
MAX
and shorting I
FB
to V
CC
.
SS (Pin 9):
Soft-Start. Connect to an external capacitor to
implement a soft-start function. During moderate over-
load conditions, the soft-start capacitor will be discharged
slowly in order to reduce the duty cycle. In hard current
limit, the soft-start capacitor will be forced low immedi-
ately and the LTC1753 will rerun a complete soft-start
cycle. C
SS
must be selected such that during power-up the
current through Q1 will not exceed the current limit value.
G2 (Pin 1):
Gate Drive for the Lower N-Channel MOSFET,
Q2. This output will swing from PV
CC
to GND. It will always
be low when G1 is high or when the output is disabled. To
prevent undershoot during a soft-start cycle, G2 is held
low until G1 first goes high.
PV
CC
(Pin 2):
Power Supply for G1 and G2. PV
CC
must be
connected to a potential of at least V
IN
+ V
GS(ON)Q1
. For
normal applications, connect PV
CC
to a 12V power supply
or generate PV
CC
using a simple charge pump.
GND (Pin 3):
Power Ground. GND should be connected to
a low impedance ground plane in close proximity to the
source of Q2.
SGND (Pin 4):
Signal Ground. SGND is connected to the
low power internal circuitry and should be connected to
the negative terminal of the output capacitor where it
returns to the ground plane. GND and SGND should be
shorted directly at the LTC1753.
V
CC
(Pin 5):
Power Supply. Power for the internal low
power circuity. V
CC
should be wired separately from the
drain of Q1 if they share the same supply. A 10
μ
F bypass
capacitor is recommended from this pin to SGND.
SENSE (Pin 6):
Output Voltage Pin. Connect to the positive
terminal of the output capacitor. There is an internal 108k
resistor connected from this pin to SGND. SENSE is a very
sensitive pin; for optimum performance, connect an exter-
nal 1
μ
F capacitor from this pin to SGND. By connecting a
small external resistor between the output capacitor and
TYPICAL PERFOR U
PIU
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