tCONV t6 DAT" />
參數(shù)資料
型號: LTC1608ACG
廠商: Linear Technology
文件頁數(shù): 3/20頁
文件大?。?/td> 0K
描述: IC A/D CONV 16BIT SAMPLNG 36SSOP
標準包裝: 37
位數(shù): 16
采樣率(每秒): 500k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 420mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 36-SSOP(0.209",5.30mm 寬)
供應商設(shè)備封裝: 36-SSOP
包裝: 管件
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,雙極
11
LTC1608
RD = CONVST
CS = 0
BUSY
1608 F08
tCONV
t6
DATA (N – 1)
D15 TO D0
DATA
DATA N
D15 TO D0
DATA (N + 1)
D15 TO D0
DATA N
D15 TO D0
t11
t8
t10
t7
RD = CONVST
BUSY
CS = 0
1608 F09
tCONV
t6
DATA (N – 1)
D15 TO D0
DATA
DATA N
D15 TO D0
t10
t11
t8
Figure 8. Mode 2. Slow Memory Mode Timing
Figure 9. ROM Mode Timing
APPLICATIO S I FOR ATIO
WU
UU
spike while charging the sample-and-hold capacitors at
the end of conversion. During conversion, the analog
inputs draw only a small leakage current. If the source
impedance of the driving circuit is low, then the LTC1608
inputs can be driven directly. As source impedance in-
creases so will acquisition time (see Figure 10). For
minimum acquisition time with high source impedance, a
buffer amplifier should be used. The only requirement is
that the amplifier driving the analog input(s) must settle
after the small current spike before the next conversion
starts (settling time must be 200ns for full throughput
rate).
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a
low output impedance (< 100
) at the closed-loop band-
width frequency. For example, if an amplifier is used in a
gain of +1 and has a unity-gain bandwidth of 50MHz, then
Figure 10. tACQ vs Source Resistance
SOURCE RESISTANCE (
)
1
10
100
1k
10k
ACQUISITION
TIME
(
s)
10
1
0.1
0.01
1608 F10
the output impedance at 50MHz should be less than
100
. The second requirement is that the closed-loop
bandwidth must be greater than 15MHz to ensure
adequate small-signal settling for full throughput rate. If
slower op amps are used, more settling time can be
provided by increasing the time between conversions.
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