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參數(shù)資料
| 型號： | LTC1428CS8-50#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC D/A CONV 8BIT SINK OUT 8-SOIC |
| 標(biāo)準包裝： | 2,500 |
| 位數(shù)： | 8 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 120µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | * |
7
LTC1428-50
Figure 5. Pulse Mode; Increment/Decrement
(2-Wire Control by CLK and UP/DN)
APPLICATIONS INFORMATION
WU
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
shifted in, a rising edge at CS transfers the data from the
input shift register into the DAC register. The DAC output
assumes the new value and the DOUT pin returns to a high-
impedance state.
IOUT = (B7 B6 B5 B4 B3 B2 B1 B0)IFULLSCALE/255
TYPICAL APPLICATION
U
Pulse Mode: Increment-Only (1-Wire Control by CLK) with Voltage Output
Figure 4. Pulse Mode: Increment Only
(1-Wire Control by CLK)
1
2
SHDN
CLK
VBIAS
RFB
100k
8
7
DOUT
DIN
DOUT
VCC
IOUT
VCC
SHDN
CLK
LTC1428-50
VDD
VEE
6
7
2
3
4
GND
CS
1428-50 TA02
VOUT
VOUT = (IOUT)(RFB) + VBIAS
VDD ≥ VOUT + 1V, 2V ≤ VBIAS ≤ 10V
3
4
6
5
–
+
LT1006
1
2
SHDN
CLK
UP/DN
8
7
DOUT
DIN
DOUT
IOUT
VCC
SHDN
CLK
LTC1428-50
GND
CS
1428-50 F05
IOUT
3
4
6
5
0.1
F
1
2
SHDN
CLK
8
7
DOUT
DIN
DOUT
IOUT
VCC
SHDN
CLK
LTC1428-50
GND
CS
1428-50 F04
IOUT
3
4
6
5
0.1
F
DAC output by one step. The last two LSBs are always zero
in pulse mode.
IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255
To configure the LTC1428-50 in 1-wire pulse mode, tie
both the CS and DIN pins to VCC.
2-Wire Interface (Pulse Mode, Figure 5)
In 2-wire pulse mode, a logic high at UP/DN programs the
DAC register to increment and each rising edge at CLK
increments the upper six bits of the register by one count.
Similarly, a logic low at UP/DN programs the DAC register
to decrement and a rising edge at CLK decrements the
upper six bits of the register by one count. Each count in
2-wire mode changes the DAC output by a single 4LSB
step. The DAC register stops incrementing at 11111100B
and stops decrementing at 00000000B and will not roll
over in 2-wire pulse mode. The last two LSBs are always
zero in pulse mode.
IOUT = (B7 B6 B5 B4 B3 B2 0 0)IFULLSCALE/255
To configure the LTC1428-50 in 2-wire pulse mode, tie CS
to VCC and bring the UP/DN pin low at least once during
power-up.
1-Wire Interface (Pulse Mode, Figure 4)
In 1-wire pulse mode, each rising edge at CLK increments
the upper six bits of the DAC register by one count. When
incremented beyond 11111100B, the counter rolls over
and sets the DAC to the minimum value (00000000B). In
this way, a single pulse applied to CLK increases the DAC
output by a single 4LSB step and 63 pulses decrease the
1
2
SHDN
CLK
CS
DIN
DOUT
8
7
DOUT
DIN
IOUT
VCC
SHDN
CLK
LTC1428-50
GND
CS
1428-50 F03
IOUT
3
4
6
5
VCC
0.1
F
DIN AND DOUT CAN BE TIED TOGETHER
FOR HALF-DUPLEX DATA TRANSFER
Figure 3. 3-Wire Mode; Serial Interface
(3-Wire Control by CS, CLK and DIN)
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