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參數(shù)資料
| 型號： | LTC1402 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Serial 12-Bit, 2.2Msps Sampling ADC with Shutdown(串行12位，2.2Msps 采樣模數(shù)轉(zhuǎn)換器(帶關(guān)斷)) |
| 中文描述： | 串行12位，2.2Msps采樣ADC（串行12位，2.2Msps采樣模數(shù)轉(zhuǎn)換器（帶關(guān)斷）與關(guān)斷） |
| 文件頁數(shù)： | 4/24頁 |
| 文件大小： | 280K |
| 代理商： | LTC1402 |
4
LTC1402
SYMBOL
f
SAMPLE(MAX)
t
THROUGHPUT
t
SCK
t
CONV
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
8a
t
9
t
10
t
11
t
12
PARAMETER
Maximum Sampling Frequency (Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Minimum Clock Period
Conversion Time
14th SCLK
↑
to CONV
↑
Interval
Minimum Positive or Negative SCK Pulse Width
CONV to SCK
Setup Time
SCK
After CONV
Minimum Positive or Negative CONV Pulse Width
SCK
to Sample Mode
CONV to Hold Mode
Minimum Delay Between Conversions
Minimum Delay from SCK
to Valid Bits 0 Through 11
Minimum Delay from SCK to Valid REFREADY
SCK to Hi-Z at D
OUT
Previous D
OUT
Bit Remains Valid After SCK
REFREADY Bit Delay After Sleep-to-Wake Transition
V
REF
Settling Time After Sleep-to-Wake Transition
CONDITIONS
MIN
2.2
TYP
MAX
UNITS
MHz
G
G
455
10000
ns
ns
G
28
(Note 9)
(Notes 9, 10, 16)
(Note 9)
(Notes 9, 13)
(Note 9)
(Note 9)
(Note 9)
(Notes 9, 14)
(Note 9)
(Notes 9, 15)
(Notes 9, 15)
(Notes 9, 15)
(Notes 9, 15)
(Notes 9, 17)
(Notes 9, 17)
14
SCK cycles
G
57
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
G
3.8
7.3
6
G
12
G
0
G
3.5
9
3.4
5
G
14
5
G
G
48
G
9
12
20
16
G
15
11.4
7
10
2
G
G
4
G
G
The
G
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. (Note 5)
SYMBOL
V
DD
V
SS
I
DD
PARAMETER
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
CONDITIONS
MIN
4.75
–5.25
TYP
MAX
5.25
0
30
5
10
2
150
UNITS
V
V
Active Mode
Nap Mode
Sleep Mode
Active, Sleep or Nap Modes with SCK Off
Active Mode with SCK in Fixed State (Hi or Lo)
G
G
18
3
2
mA
mA
μ
A
μ
A
mW
I
SS
PD
Negative Supply Current
Power Dissipation
G
90
POWER REQUIRE E TS
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with DGND, AGND1
and AGND2 wired together.
Note 3:
When these pins are taken below V
SS
or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below V
SS
or greater than V
DD
without latchup.
Note 4:
When these pins are taken below V
SS
, they will be clamped by
internal diodes. This product can handle input currents greater than
100mA below V
SS
or greater than V
DD
. These pins are not clamped to V
DD
.
Note 5:
V
DD
= 5V, f
SAMPLE
= 2.2MHz, V
SS
= 0V for unipolar mode
specifications and V
SS
= –5V for bipolar specifications.
The
G
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25
°
C. (Note 5)
Note 6:
Linearity, offset and full-scale specifications apply for a single-
ended A
IN+
input with A
IN–
grounded and using the internal reference in
bipolar mode with
±
5V supplies.
Note 7:
Integral linearity is defined as the deviation of a code from the
straight line passing through the actual endpoints of a transfer curve. The
deviation is measured from the center of quantization band.
Note 8:
Bipolar offset is the offset measured from –0.5LSB when the input
flickers between 1000 0000 0000 and 0111 1111 1111.
Note 9:
Guaranteed by design, not subject to test.
Note 10:
Recommended operating conditions.
Note 11:
The analog input range is defined as the voltage difference
between A
IN+
and A
IN–
. The bipolar
±
2.048V input range could be used
with a single 5V supply if the absolute voltages of the inputs remain within
the single 5V supply voltage.
TI I G CHARACTERISTICS
U
W
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