DIN DOUT “+” IN" />
參數(shù)資料
型號： LTC1199LIS8#PBF
廠商： Linear Technology
文件頁數(shù)： 9/28頁
文件大小： 0K
描述： IC ADC 10BIT 210KHZ W/SD 8-SOIC
標準包裝： 100
位數(shù)： 10
采樣率（每秒）： 210k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 25mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應商設備封裝： 8-SOIC
包裝： 管件
輸入數(shù)目和類型： 1 個單端，單極
17
LTC1197/LTC1197L
LTC1199/LTC1199L
CLK
DIN
DOUT
“+” INPUT
“–” INPUT
SAMPLE
HOLD
“+” INPUT MUST
SETTLE DURING
THIS TIME
tSMPL
tCONV
CS
SGL/DIFF
START
DUMMY
ODD/SGN
DON‘T CARE
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
1197/99 F05
Figure 5. LTC1199/LTC1199L “+” and “–” Input Settling Windows
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1197/
LTC1197L/LTC1199/LTC1199L have capacitive switching
input current spikes. These current spikes settle quickly
and do not cause a problem if source resistances are less
than 200
or high speed op amps are used (e.g., the
LT
1224, LT1191, LT1226 or LT1215). However, if large
source resistances are used or if slow settling op amps
drive the inputs, take care to ensure that the transients
caused by the current spikes settle completely before the
conversion begins.
“+” Input Settling
The input capacitor of the LTC1197/LTC1197L is switched
onto the “+” input in the falling edge of CS and the sample
time continues until the second falling CLK edge (see
Figure 1). However, the input capacitor of the LTC1199/
LTC1199L is switched onto “+” input after ODD/SGN is
clocked into the ADC and remains there until the fourth
falling CLK edge (see Figure 5). The sample time is 1.5 CLK
cycles before conversion starts. The voltage on the “+”
Figure 6. Analog Equivalent Circuit
input must settle completely within tSMPL for the ADC to
perform an accurate conversion. Minimizing RSOURCE+
and C1 will improve the input settling time (see Figure 6).
If a large “+” input source resistance must be used, the
sample time can be increased by using a slower CLK
frequency.
“–” Input Settling
At the end of tSMPL, the input capacitor switches to the
“–” input and conversion starts (see Figures 1 and 5).
During the conversion the “+” input voltage is effectively
“held” by the sample-and-hold and will not affect the
APPLICATIO S I FOR ATIO
WU
UU
RON = 200
CIN = 20pF
LTC1197/LTC1197L
LTC1199/LTC1199L
“+”
INPUT
RSOURCE
+
VIN
+
C1
“–”
INPUT
RSOURCE
–
VIN
–
C2
1197/99 F06
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