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參數(shù)資料
| 型號(hào)： | LTC1199LIS8#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT 210KHZ W/SD 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 210k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)單端，單極 |
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13
LTC1197/LTC1197L
LTC1199/LTC1199L
1197/99 F02
CLK
CS
tdDO
tsuCS
B0*
B1
B2
B3
B4
B5
B6
B7
B8
B9
NULL
BITS
Hi-Z
14
13
12
11
10
9
8
7
6
5
4
3
2
1
15
16
1
DOUT
DIN
HI-Z
START
DUMMY
DON’T CARE
ODD/
SIGN
SGL/
DIFF
*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW,
THE ADC WILL OUTPUT ZEROS INDEFINITELY
ten
tCYC (16 CLKs)*
tCONV
(10.5 CLKs)
POWER
DOWN
tSMPL
(1.5 CLKs)
Figure 2. LTC1199/LTC1199L Operating Sequence
transfer and all leading zeros that precede this logical one
will be ignored. After the start bit is received the remaining
bits of the input word will be clocked in. Further inputs on
the DIN pin are then ignored until the next CS cycle.
Multiplexer (MUX) Address
The bits of the input word following the start bit assign the
MUX configuration for the requested conversion. For a
given channel selection, the converter will measure the
voltage between the two channels indicated by the “+” and
“–” signs in the selected row of the following table. In
single-ended mode, all input channels are measured with
respect to GND. Only the + inputs have sample-and-holds.
Signals applied at the – inputs must not change more than
the required accuracy during the conversion.
Multiplexer Channel Selection
MUX ADDRESS
SGL/DIFF
1
0
ODD/SIGN
0
1
0
1
CHANNEL #
0
+
–
1
+
–
+
GND
–
1197/99 AI02
The LTC1197/LTC1197L do not require a configuration
input word and have no DIN pin. A falling CS initiates data
transfer as shown in the LTC1197/LTC1197L operating
sequence. After CS falls, the second CLK pulse enables
DOUT. After two null bits, the A/D conversion result is output
on the DOUT line in MSB-first format. Bringing CS high
resets the LTC1197/LTC1197L for the next data exchange
and minimizes the supply current if CLK is continuously
running.
INPUT DATA WORD (LTC1199/LTC1199L ONLY)
The LTC1199 4-bit data word is clocked into the DIN input
on the rising edge of the clock after CS goes low and the
start bit has been recognized. Further inputs on the DIN pin
are then ignored until the next CS cycle. The input word is
defined as follows:
SGL/
DIFF
ODD/
SIGN
DUMMY
START
MUX
ADDRESS
1197/99 AI01
Start Bit
The first “l(fā)ogical one” clocked into the DIN input after CS
goes low is the start bit. The start bit initiates the data
APPLICATIO S I FOR ATIO
WU
UU
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