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參數(shù)資料
| 型號： | LTC1090CSW#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DATA ACQUIS SYS 10BIT 20-SOIC |
| 標準包裝： | 38 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS），ADC |
| 分辨率（位）： | 10 b |
| 采樣率（每秒）： | 30k |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 單/雙電源 |
| 電源電壓： | ±5V，5V，10V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 管件 |
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20
LTC1090
1090fc
Input Op Amps
When driving the analog inputs with an op amp it is
important that the op amp settle within the allowed time
(see Figure 10). Again, the “+” and “–” input sampling
times can be extended as described above to accommo-
date slower op amps. Most op amps including the LT1006
and LT1013 single supply op amps can be made to settle
well even with the minimum settling windows of 4s (“+”
input) and 2s (“–” input) which occur at the maximum
clock rates (ACLK = 2MHz and SCLK = 1MHz). Figures 11
and 12 show examples of adequate and poor op amp
settling.
RC Input Filtering
It is possible to filter the inputs with an RC network as
shown in Figure 13. For large values of CF (e.g., 1F), the
capacitive input switching currents are averaged into a net
DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops
across the resistor. The magnitude of the DC current is
approximately lDC = 60pF x VIN/tCYC and is roughly propor-
tional to VIN. When running at the minimum cycle time of
33s, the input current equals 9A at VIN = 5V. In this case,
a filter resistor of 50 will cause 0.1LSB of full-scale error.
If a larger filter resistor must be used, errors can be
eliminated by increasing the cycle time as shown in the
typical curve of Maximum Filter Resistor vs Cycle Time.
Figure 11. Adequate Settling of Op Amp Driving Analog Input
Figure 12. Poor Op Amp Settling can Cause A/D Errors
Figure 13. RC Input Filtering
APPLICATIO S I FOR ATIO
WU
UU
HORIZONTAL: 1s/DIV
VERTICAL:
5mV/DIV
HORIZONTAL: 20s/DIV
VERTICAL:
5mV/DIV
LTC1090 AI18
VIN
RFILTER
IDC
CFILTER
LTC1090
“ + ”
“ – ”
Input Leakage Current
Input leakage currents can also create errors if the source
resistance gets too large. For instance, the maximum input
leakage specification of 1A (at 125°C) flowing through a
source resistance of 1k will cause a voltage drop of 1mV
or 0.2LSB. This error will be much reduced at lower
temperatures because leakage drops rapidly (see typical
curve of Input Channel Leakage Current vs Temperature).
Noise Coupling into Inputs
High source resistance input signals (>500) are more
sensitive to coupling from external sources. It is preferable
to use channels near the center of the package (i.e., CH2 to
CH7) for signals which have the highest output resistance
because they are essentially shielded by the pins on the
package ends (DGND and CH0). Grounding any unused
inputs (especially the end pin, CH0) will also reduce
outside coupling into high source resistances.
4. Sample-and-Hold
Single Ended Inputs
The LTC1090 provides a built-in sample and hold (S&H)
function for all signals acquired in the single ended mode
(COM pin grounded). This sample and hold allows the
LTC1090 to convert rapidly varying signals (see typical
curve of S&H Acquisition Time vs Source Resistance). The
input voltage is sampled during the tSMPL time as shown
in Figure 10. The sampling interval begins after the fourth
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