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參數(shù)資料
| 型號(hào)： | LTC1040CSW#TRPBF |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR LOW PWR DUAL18SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | LTCMOS™ |
| 類型： | 通用 |
| 元件數(shù)： | 2 |
| 輸出類型： | CMOS，TTL |
| 電壓 - 電源，單路/雙路(±)： | 2.8 V ~ 16 V，±2.8 V ~ 8 V |
| 電壓 - 輸入偏移（最小值）： | 4.5mV @ ±8V |
| 電流 - 輸入偏壓（最小值）： | 300pA @ ±5V |
| 電流 - 靜態(tài)（最大值）： | 3mA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 18-SOIC（0.295"，7.50mm 寬） |
| 安裝類型： | 表面貼裝 |
| 包裝： | 帶卷 (TR) |
7
LTC1040
1040fa
1A
100mV
APPLICATIO S I FOR ATIO
WU
UU
Offset Voltage Error
The errors due to offset, common mode, power supply
variation, gain and temperature are all included in the
offset voltage specification. This makes it easy to compute
the error when using the LTC1040.
Example: error computation for Figure 4.
Assume: 2.8V
≤ VS ≤ 6V.
Then total worst-case error is:
Note: If source resistance exceeds 10k, bypass
capacitors should be used and the associated errors must
be included.
Pulsed Power (VP-P) Output
It is often desirable to use comparators with resistive
networks such as bridges. Because of the extremely low
power consumption of the LTC1040, the power consumed
by these resistive networks can far exceed that of the
device itself.
At low sample rates the LTC1040 spends most of its time
off. To take advantage of this, a pulsed power (VP-P) output
is provided. VP-P is switched to V+ when the comparator
is on and to a high impedance (open circuit) when the
comparator is off. The ON time is nominally 80
s.
Figure 5 shows the VP-P output circuit.
The VP-P output voltage is not precise (see VP-P Output
Voltage versus Load Current curve). There are two ways
VP-P can be used to power external networks without
excessive errors: (1) ratiometric networks and (2) fast
settling references.
In a ratiometric network, the inputs are all proportional to
VP-P (see Figure 6). Consequently, for small changes, the
absolute value of VP-P does not affect accuracy.
It is critical that the inputs to the LTC1040 completely
settle within 4
s of the start of the comparison cycle and
that they do not change during the 80
s ON time. When
driving resistive networks with VP-P, capacitive loading on
the network should be minimized to meet the 4
s settling
time requirement. It is not recommended that VP-P be used
to drive networks with source impedances, as seen by the
inputs, of greater than 10k
.
In applications where an absolute reference is required,
the VP-P output can be used to drive a fast settling
reference. The LT1009 2.5V reference, ideal in this
application, settles in approximately 2
s (see Figure 7).
The current through R1 must be large enough to supply
the LT1009 minimum bias current (
≈1mA) and the load
current, IL.
LTC1040 AI05
80
s
COMPARATOR ON TIME
18
V+
917
GND
Q1 P1
VP-P
Figure 7. Driving Reference with VP-P Output
Figure 6. Ratiometric Network Driven by VP-P
Figure 5. VP-P Output Switch
=
±6mA
IL (ERROR) = ± (100mV 0.001 + 0.5mV)
↑↑
Tracking Error
VOS
IL (ERROR)% =
100 =
± 0.6%.
6mA
1A
VIN
VTRIP
OUTPUT
VP-P OUTPUT
LTC1040 AI06
–
–+
–
+
1/2
LTC1040
VIN
IL
VP-P OUTPUT
LTC1040 AI07
–
+
1/2
LTC1040
R2
R3
LT1009
R1
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