參數(shù)資料
型號(hào): LT8410EDC-1#PBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.01 A SWITCHING REGULATOR, PDSO8
封裝: 2 X 2 MM, LEAD FREE, PLASTIC, DFN-8
文件頁(yè)數(shù): 14/16頁(yè)
文件大?。?/td> 309K
代理商: LT8410EDC-1#PBF
LT8410/LT8410-1
7
84101fb
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Pin. This pin is used to enable/
disablethechip.Drivebelow0.3Vtodisablethechip.Drive
above 1.45V to activate the chip. Do not float this pin.
VCC (Pin 2): Input Supply Pin. Must be locally bypassed
to GND. See the Typical Applications section.
GND (Pin 3): Ground. Tie directly to local ground plane.
SW (Pin 4): Switch Pin. This is the collector of the inter-
nal NPN power switch. Minimize the metal trace area
connected to this pin to minimize EMI.
VOUT (Pin 5): Drain of Output Disconnect PMOS. Place
a bypass capacitor from this pin to GND.
CAP (Pin 6): Cathode of the Internal Schottky Diode. Place
a bypass capacitor from this pin to GND.
VREF (Pin 7): Reference Pin. Soft-start can be achieved
by placing a capacitor from this pin to GND. This cap
will be discharged for 70s (typical) at the beginning
of start-up and then be charged to 1.235V with a 10μA
current source.
FBP (Pin 8): Positive Feedback Pin. This pin is the error
amplifier’s positive input terminal. To achieve the desired
output voltage, choose the FBP pin voltage (VFBP) accord-
ing to the following formula:
VFBP =
VOUT
31.85
Forprotectionpurposes,theoutputvoltagecannotexceed
40V even if VFBP is driven higher than VREF.
Exposed Pad (Pin 9): Pin 9 is floating but must be ground-
ed for proper shielding.
BLOCK DIAGRAM
2
7
8
9
+
DISCHARGE
CONTROL
ENABLE
CHIP
1.235V
VREF
VCC
FBP
FB
VC
GND
EXPOSED PAD
(GND)
400k
CAP
MAX
10A
SW
SHDN
12.4M
VOUT
SWITCH
CONTROL
+
TIMING AND PEAK
CURRENT CONTROL
+
1
1.235V
3
5
6
4
OUTPUT DISCONNECT
CONTROL
1.235V
+
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