參數(shù)資料
型號(hào): LT3724MPFE#TR
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 225 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 4.40 MM, PLASTIC, TSSOP-16
文件頁(yè)數(shù): 23/26頁(yè)
文件大?。?/td> 309K
代理商: LT3724MPFE#TR
LT3724
6
3724fd
PIN FUNCTIONS
VIN (Pin 1): The VIN pin is the main supply pin and should
be decoupled to SGND with a low ESR capacitor located
close to the pin.
NC (Pin 2): No Connection.
SHDN (Pin 3): The SHDN pin has a precision IC enable
threshold of 1.35V (rising) with 120mV of hysteresis. It is
usedtoimplementanundervoltagelockout(UVLO)circuit.
See Application Information section for implementing a
UVLO function. When the SHDN pin is pulled below a
transistor VBE (0.7V), a low current shutdown mode is
entered, all internal circuitry is disabled and the VIN sup-
ply current is reduced to approximately 10A. Typical
pin input bias current is <10A and the pin is internally
clamped to 6V.
CSS (Pin 4): The soft-start pin is used to program the sup-
ply soft-start function. The pin is connected to VOUT via a
ceramic capacitor (CSS)and200kΩseriesresistor.During
start-up, the supply output voltage slew rate is controlled
to produce a 2A average current through the soft-start
coupling capacitor. Use the following formula to calculate
CSS for a given output voltage slew rate:
CSS = 2A(tSS/VOUT)
Seetheapplicationsectionformoreinformationonsetting
therisetimeoftheoutputvoltageduringstart-up.Shorting
this pin to SGND disables the soft-start function.
BURST_EN (Pin 5): The BURST_EN pin is used to enable
or disable Burst Mode operation. Connect the BURST_EN
pin to ground to enable the burst mode function. Connect
the pin to VCC to disable the burst mode function.
VFB (Pin 6): The output voltage feedback pin, VFB, is
externally connected to the supply output voltage via a
resistive divider. The VFB pin is internally connected to
the inverting input of the error amplifier. In regulation,
VFB is 1.231V.
VC (Pin 7): The VC pin is the output of the error amplifier
whosevoltagecorrespondstothemaximum(peak)switch
current per oscillator cycle. The error amplifier is typically
configured as an integrator circuit by connecting an RC
network from the VC pin to SGND. This circuit creates the
dominant pole for the converter regulation control loop.
Specific integrator characteristics can be configured to
optimizetransientresponse.Connectinga100pForgreater
high frequency bypass capacitor from this pin to ground
is recommended. When Burst Mode operation is enabled
(see Pin 5 description), an internal low impedance clamp
on the VC pin is set at 100mV below the burst threshold,
which limits the negative excursion of the pin voltage.
Therefore, this pin cannot be pulled low with a low imped-
ance source. If the VC pin must be externally manipulated,
do so through a 1kΩ series resistance.
SGND (Pin 8, 17): The SGND pin is the low noise ground
reference. It should be connected to the –VOUT side of the
output capacitors. Careful layout of the PCB is necessary
to keep high currents away from this SGND connection.
See the Application Information section for helpful hints
on PCB layout of grounds.
SENSE(Pin 9): The SENSEpin is the negative input for
the current sense amplifier and is connected to the VOUT
side of the sense resistor for step-down applications. The
sensed inductor current limit is set to 150mV across the
SENSE inputs.
SENSE+ (Pin 10): The SENSE+ pin is the positive input for
the current sense amplifier and is connected to the induc-
tor side of the sense resistor for step-down applications.
The sensed inductor current limit is set to 150mV across
the SENSE inputs.
PGND (Pin 11): The PGND pin is the high-current ground
referenceforinternallowsideswitchandtheVCCregulator
circuit. Connect the pin directly to the negative terminal of
theVCCdecouplingcapacitor.SeetheApplicationInforma-
tion section for helpful hints on PCB layout of grounds.
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