參數資料
型號: LT3692IUH#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 5.8 A DUAL SWITCHING CONTROLLER, 2750 kHz SWITCHING FREQ-MAX, PQCC32
封裝: 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD, QFN-32
文件頁數: 3/36頁
文件大?。?/td> 526K
代理商: LT3692IUH#TRPBF
LT3692
11
3692f
BLOCK DIAGRAM
In addition, the internal slope compensation will be au-
tomatically adjusted to prevent subharmonic oscillation
during synchronization. In either mode of oscillator op-
eration, a square wave with the master clock frequency,
synchronized to channel 1 is present at the CLKOUT pin.
The two regulators are constant frequency, current mode
step-down converters. Current mode regulators are con-
trolled by an internal clock and two feedback loops that
control the duty cycle of the power switch. In addition to
thenormalerroramplifier,thereisacurrentsenseamplifier
that monitors switch current on a cycle-by-cycle basis.
This technique means that the error amplifier commands
current to be delivered to the output rather than voltage.
A voltage fed system will have low phase shift up to the
resonant frequency of the inductor and output capacitor,
then an abrupt 180° shift will occur. The current fed sys-
tem will have 90° phase shift at a much lower frequency,
but will not have the additional 90° shift until well beyond
the LC resonant frequency. This makes it much easier to
frequency compensate the feedback loop and also gives
much quicker transient response.
The Block Diagram in Figure 1 shows only one of the
switching regulators whose operation will be discussed
below. The additional regulator will operate in a similar
manner with the exception that its clock will be 180° out
of phase with the other regulator.
When, during power-up, an internal POR signal sets the
soft-start latch, both SS pins will be discharged to ground
to ensure proper start-up operation. When the SS pin volt-
age drops below 90mV, the VC pin is driven low disabling
switching and the soft-start latch is reset. Once the latch
is reset the soft-start capacitor starts to charge with a
typical value of 12A.
As the voltage rises above 115mV on the SS pin, the VC
pin will be driven high by the error amplifier. When the
voltageontheVCpinexceeds0.8V,theclockset-pulsesets
the driver flip-flop, which turns on the internal power NPN
switch. This causes current from VIN, through the NPN
switch, inductor and internal sense resistor to increase.
When the voltage drop across the internal sense resistor
exceeds a predetermined level set by the voltage on the
VC pin, the flip-flop is reset and the internal NPN switch
is turned off. Once the switch is turned off the inductor
will drive the voltage at the SW pin low until the external
Schottky diode starts to conduct, decreasing the current
in the inductor. The cycle is repeated with the start of each
clock cycle. However, if the internal sense resistor voltage
exceedsthepredeterminedlevelatthestartofaclockcycle,
the flip-flop will not be set resulting in a further decrease
in inductor current. Since the output current is controlled
by the VC voltage, output regulation is achieved by the
error amplifier continually adjusting the VC pin voltage.
The error amplifier is a transconductance amplifier that
compares the FB voltage to the lowest voltage present at
either the SS pin or an internal 806mV reference. Compen-
sation of the loop is easily achieved with a simple capacitor
or series resistor/capacitor from the VC pin to ground.
The regulators’ maximum output current occurs when the
VC pin is driven to its maximum clamp value by the error
amplifier. The value of the maximum switch current can be
programmed from 4.8A to 2A by placing a resistor from
the ILIM pin to ground.
Since the SS pin is driven by a constant current source, a
singlecapacitoronthesoft-startpinwillgeneratecontrolled
linear ramp on the output voltage.
If the current demanded by the output exceeds the maxi-
mum current dictated by the VC pin clamp, the SS pin
will be discharged, lowering the regulation point until the
output voltage can be supported by the maximum current.
Once the overload condition is removed, the regulator will
soft-start from the overload regulation point.
Shutdown control, VINovervoltage,orthermalshutdown
will set the soft-start latch, resulting in a complete soft-
start sequence.
The switch driver operates from either the VIN or BST volt-
age. An external diode and capacitor are used to generate
a drive voltage higher than VIN to saturate the output NPN
and maintain high efficiency. If the BST capacitor voltage
is sufficient, the switch is allowed to operate to 100% duty
cycle. If the boost capacitor discharges towards a level
insufficient to drive the output NPN, a BST pin compara-
tor forces a minimum cycle off time, allowing the boost
capacitor to recharge.
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