參數(shù)資料
型號: LT3692IUH#TRPBF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 5.8 A DUAL SWITCHING CONTROLLER, 2750 kHz SWITCHING FREQ-MAX, PQCC32
封裝: 5 X 5 MM, LEAD FREE, PLASTIC, MO-220WHHD, QFN-32
文件頁數(shù): 11/36頁
文件大?。?/td> 526K
代理商: LT3692IUH#TRPBF
LT3692
19
3692f
APPLICATIONS INFORMATION
Ifthesynchronizationsignalpowersupinanundetermined
state (VOL, VOH, Hi-Z), connect the synchronization clock
to the LT3692 as shown in Figure 9. The circuit as shown
will isolate the synchronization signal when the output
voltage is below 90% of the regulated output. The LT3692
will start up with a switching frequency determined by the
resistor from the RT/SYNC pin to ground.
Ifthesynchronizationsignalpowersupinalowimpedance
state (VOL), connect a resistor between the RT/SYNC pin
and the synchronizing clock. The equivalent resistance
seen from the RT/SYNC pin to ground will set the start-
up frequency.
If the synchronization signal powers up in a high imped-
ance state (Hi-Z), connect a resistor from the RT/SYNC
pin to ground. The equivalent resistance seen from the
RT/SYNC pin to ground will set the start-up frequency.
Reducing Input Ripple Voltage
Synchronizing the switches to the rising and falling edges
of the synchronization signal provides the unique ability to
reduceinputripplecurrentsinsystemswhereVIN1andVIN2
are connected to the same supply. Decreasing the input
current ripple reduces the required input capacitance. For
example, the input ripple voltage shown in Figure 12 for
a typical antiphase dual 14.4V to 8.5V and 14.4V to 3.3V
regulator is decreased from a peak of 472mV to 160mV
as shown in Figure 13 by driving the LT3692 with a 71%
duty cycle synchronization signal.
Figure 9. Synchronous Signal Powered from Regulator’s Output
Figure 10. Timing Diagram RT/SYNC = 1MHz, Duty Cycle = 50%
Figure 11. Timing Diagram RT/SYNC = 1MHz, Duty Cycle > 50%
Figure 12. Dual 14.4V/8.5V, 14.4V/3.3V with 180° Phase
Figure 13. Dual 14.4V/8.5V, 14.4V/3.3V with 256° Phase
tP
tP/2
tP
tP/2
tDCLKOSW2
tDRTSYNC
tDCLKOSW1
SW1
SW2
CLKOUT
RT/SYNC
3692 F10
tP
tDCLKOSW2
tDCLKOSW1
SW1
SW2
CLKOUT
RT/SYNC
tDRTSYNCH
3692 F11
tP
tPON
tP
LT3692
SYNCHRONIZATION
CIRCUITRY
VOUT1
RT/SYNC
3692 F09
VCC
CLK
PG1
SW1
SW2
RT/SYNC
3692 F12
INPUT
RIPPLE V
SW1
SW2
RT/SYNC
INPUT
RIPPLE V
3692 F13
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