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參數資料
| 型號： | LT1739CFE |
| 廠商： | Linear Technology |
| 文件頁數： | 4/20頁 |
| 文件大小： | 0K |
| 描述： | IC AMP XDSL LINE DRV DUAL20TSSOP |
| 標準包裝： | 74 |
| 類型： | 線路驅動器，發(fā)射器 |
| 驅動器/接收器數： | 2/0 |
| 規(guī)程： | DSL |
| 電源電壓： | 5 V ~ 12 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬）裸露焊盤 |
| 供應商設備封裝： | 20-TSSOP-EP |
| 包裝： | 管件 |
12
LT1739
1739fas, sn1739
Layout and Passive Components
With a gain bandwidth product of 200MHz the LT1739
requires attention to detail in order to extract maximum
performance. Use a ground plane, short lead lengths and
a combination of RF-quality supply bypass capacitors (i.e.,
0.1
F). As the primary applications have high drive cur-
rent, use low ESR supply bypass capacitors (1
F to 10F).
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with the
input capacitance to form a pole that can cause frequency
peaking. In general, use feedback resistors of 1k or less.
Compensation
The LT1739 is stable in a gain 10 or higher for any supply
and resistive load. It is easily compensated for lower gains
with a single resistor or a resistor plus a capacitor.
Figure 9 shows that for inverting gains, a resistor from the
inverting node to AC ground guarantees stability if the
parallel combination of RC and RG is less than or equal to
RF/9. For lowest distortion and DC output offset, a series
capacitor, CC, can be used to reduce the noise gain at
lower frequencies. The break frequency produced by RC
and CC should be less than 5MHz to minimize peaking.
Figure 10 shows compensation in the noninverting con-
figuration. The RC, CC network acts similarly to the invert-
ing case. The input impedance is not reduced because the
network is bootstrapped. This network can also be placed
between the inverting input and an AC ground.
Another compensation scheme for noninverting circuits is
shown in Figure 11. The circuit is unity gain at low
frequency and a gain of 1 + RF/RG at high frequency. The
DC output offset is reduced by a factor of ten. The
techniques of Figures 10 and 11 can be combined as
shown in Figure 12. The gain is unity at low frequencies,
1 + RF/RG at mid-band and for stability, a gain of 10 or
greater at high frequencies.
Figure 9. Compensation for Inverting Gains
APPLICATIO S I FOR ATIO
WU
UU
RG
RC
VO
VI
CC
(OPTIONAL)
–
+
1739 F09
RF
=
–RF
RG
VO
VI
< 5MHz
1
2
πRCCC
(RC || RG) ≤ RF/9
RC
VO
VI
CC
(OPTIONAL)
+
–
1739 F10
RF
RG
= 1 +
RF
RG
VO
VI
< 5MHz
1
2
πRCCC
(RC || RG) ≤ RF/9
Figure 10. Compensation for Noninverting Gains
+
–
1739 F11
RF
RG
Vi
VO
CC
< 5MHz
1
2
πRGCC
RG ≤ RF/9
= 1 (LOW FREQUENCIES)
(HIGH FREQUENCIES)
VO
VI
= 1 +
RF
RG
Figure 11. Alternate Noninverting Compensation
RC
VO
VI
CC
+
–
1739 F12
RF
RG
CBIG
RF
RG
= 1 AT LOW FREQUENCIES
= 1 +
AT MEDIUM FREQUENCIES
RF
(RC || RG)
= 1 +
AT HIGH FREQUENCIES
VO
VI
Figure 12. Combination Compensation
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LT1739CFE#PBF | 功能描述:IC AMP LINE DVR DUAL 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:27 系列:- 類型:收發(fā)器 驅動器/接收器數:3/3 規(guī)程:RS232，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| LT1739CFE#TR | 功能描述:IC AMP XDSL LINE DRV DUAL20TSSOP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:27 系列:- 類型:收發(fā)器 驅動器/接收器數:3/3 規(guī)程:RS232，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| LT1739CFE#TRPBF | 功能描述:IC AMP XDSL LINE DRV DUAL20TSSOP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:27 系列:- 類型:收發(fā)器 驅動器/接收器數:3/3 規(guī)程:RS232，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
| LT1739CUE | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Dual 500mA, 200MHz xDSL Line Driver Amplifier |
| LT1739CUE#PBF | 功能描述:IC OP AMP XDSL DVR 500MA 12DFN RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:* 標準包裝:27 系列:- 類型:收發(fā)器 驅動器/接收器數:3/3 規(guī)程:RS232，RS485 電源電壓:4.75 V ~ 5.25 V 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC 包裝:管件 |
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