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參數(shù)資料
| 型號： | LT1641CS8-2#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 174K |
| 代理商： | LT1641CS8-2#PBF |
5
LT1641-1/LT1641-2
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PI FU CTIO S
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ON (Pin 1): The ON pin is used to implement undervoltage
lockout. When the ON pin is pulled below the 1.233V High-
to-Low threshold voltage, an undervoltage condition is
detected and the GATE pin is pulled low to turn the
MOSFET off. When the ON pin rises above the 1.313V
Low-to-High threshold voltage, the MOSFET is turned on
again.
Pulsing the ON pin low after a current limit fault will reset
the fault latch and allow the part to turn back on.
FB (Pin 2): Power Good Comparator Input. It monitors the
output voltage with an external resistive divider. When the
voltage on the FB pin is lower than the High-to-Low
threshold of 1.233V, the PWRGD pin is pulled low and
released when the FB pin is pulled above the 1.313V Low-
to-High threshold.
The FB pin also effects foldback current limit (see Figure 7
and related discussion).
PWRGD (Pin 3): Open Collector Output to GND. The
PWRGD pin is pulled low whenever the voltage at the FB
pin falls below the High-to-Low threshold voltage. It goes
into a high impedance state when the voltage on the FB pin
exceeds the Low-to-High threshold voltage. An external
pull-up resistor can pull the pin to a voltage higher or lower
than VCC.
GND (Pin 4): Chip Ground.
TIMER (Pin 5): Timing Input. An external timing capacitor
at this pin programs the maximum time the part is allowed
to remain in current limit.
When the part goes into current limit, an 77
A pull-up
current source starts to charge the timing capacitor. When
the voltage on the TIMER pin reaches 1.233V, the GATE
pin is pulled low; the pull-up current will be turned off and
the capacitor is discharged by a 3
A pull-down current.
When the TIMER pin falls below 0.5V, the GATE pin either
turns on automatically (LT1641-2) or turns on once the
ON pin is pulsed low to reset the internal fault latch
(LT1641-1). If the ON pin is not cycled low, the GATE pin
remains latched off. Use no less than 1.5nF for the timing
capacitor, C2.
GATE (Pin 6): The High Side Gate Drive for the External
N-Channel. An internal charge pump guarantees at least
10V of gate drive for supply voltages above 20V and 4.5V
gate drive for supply voltages between 10.8V and 20V. The
rising slope of the voltage at the GATE is set by an external
capacitor connected from the GATE pin to GND and an
internal 10
A pull-up current source from the charge
pump output.
When the current limit is reached, the GATE pin voltage will
be adjusted to maintain a constant voltage across the
sense resistor while the timer capacitor starts to charge.
If the TIMER pin voltage exceeds 1.233V, the GATE pin will
be pulled low.
The GATE pin is pulled to GND whenever the ON pin is
pulled low, the VCC supply voltage drops below the 8.3V
undervoltage lockout threshold or the TIMER pin rises
above 1.233V.
SENSE (Pin 7): The Current Limit Sense Pin. A sense
resistor must be placed in the supply path between VCC
and SENSE. The current limit circuit will regulate the
voltage across the sense resistor (VCC – VSENSE) to 47mV
when VFB is 0.5V or higher. If VFB drops below 0.5V, the
voltage across the sense resistor decreases linearly and
stops at 12mV when VFB is 0V.
To defeat current limit, short the SENSE pin to the VCC pin.
VCC (Pin 8): The Positive Supply Input ranges from 9V to
80V for normal operation. ICC is typically 2mA. An internal
undervoltage lockout circuit disables the chip for inputs
less than 8.3V.
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