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參數(shù)資料
| 型號(hào)： | LT1641CS8-2#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-8 |
| 文件頁(yè)數(shù)： | 12/12頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | LT1641CS8-2#PBF |
9
LT1641-1/LT1641-2
164112fc
APPLICATIO S I FOR ATIO
WU
U
Figure 8. Response Time to Overcurrent
12mV
0V
0.5V
VFB
1641-1 F07
47mV
VCC – VSENSE
Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage
50mV
100mV
150mV
200mV
1641-1 F08
12
s
10
s
8
s
6
s
4
s
2
s
PROPAGATION DELAY
VCC – VSENSE
current source. When the TIMER pin falls below 0.5V, the
GATE pin either turns on automatically (LT1641-2) or once
the ON pin is pulsed low to reset the internal fault latch
(LT1641-1).
The waveform in Figure 9 shows how the output latches off
following a short-circuit. The drop across the sense resis-
tor is held at 12mV as the timer ramps up. Since the output
did not rise bringing FB above 0.5V, the circuit latches off.
For Figure 9, CT = 100nF.
Undervoltage and Overvoltage Detection
The ON pin can be used to detect an undervoltage condi-
tion at the power supply input. The ON pin is internally
connected to an analog comparator with 80mV of hyster-
esis. If the ON pin falls below its threshold voltage (1.233V),
the GATE pin is pulled low and is held low until ON is high
again.
Figure 10 shows an overvoltage detection circuit. When
the input voltage exceeds the Zener diode’s breakdown
voltage, D2 turns on and starts to pull the TIMER pin high.
After the TIMER pin is pulled higher than 1.233V, the fault
latch is set and the GATE pin is pulled to GND immediately,
turning off transistor Q1. The waveforms are shown in
Figure 11. Operation is restored either by interrupting
power or by pulsing ON low.
Power Good Detection
The chip includes a comparator for monitoring the output
voltage. The noninverting input (FB pin) is compared
against an internal 1.233V precision reference and exhib-
its 80mV hysteresis. The comparator’s output (PWRGD
pin) is an open collector capable of operating from a pull-
up as high as 100V.
The PWRGD pin can be used to directly enable/disable a
power module with an active high enable input. Figure 12
shows how to use the PWRGD pin to control an active low
enable input power module. Signal inversion is accom-
plished by transistor Q2 and R7.
Supply Transient Protection
The IC is 100% tested and guaranteed to be safe from
damage with supply voltages up to 100V. However, spikes
above 100V may damage the part. During a short-circuit
condition, the large change in currents flowing through
the power supply traces can cause inductive voltage
spikes which could exceed 100V. To minimize the spikes,
the power trace parasitic inductance should be minimized
by using wider traces or heavier trace plating and a 0.1
F
bypass capacitor placed between VCC and GND. A surge
suppressor at the input can also prevent damage from
voltage surges.
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