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參數(shù)資料
| 型號(hào)： | LT1508IN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Power Factor and PWM Controller(Voltage Mode) |
| 中文描述： | 1.5 A POWER FACTOR CONTROLLER WITH POST REGULATOR, 300 kHz SWITCHING FREQ-MAX, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁(yè)數(shù)： | 7/16頁(yè) |
| 文件大?。?/td> | 337K |
| 代理商： | LT1508IN |
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7
LT1508
R
SET
(Pin 15):
A resistor from R
SET
to GND sets the
oscillator charging current and the maximum multiplier
output current which is used to limit the maximum line
current.
I
M(MAX)
= 3.75V/R
SET
SS1 (Pin 16):
Soft Start. SS1 is reset to zero for low V
CC
.
When V
CC
rises above the lockout threshold, SS1 is
released to ramp up at a rate set by the internal 12
μ
A
current source and an external capacitor. During this ramp
up, PFC reference voltage is equal to SS1 voltage. After
SS1 rises past 7.5V, reference voltage remains at 7.5V.
V
CC
(Pin 17):
This is the supply for the chip. The LT1508
has two fast gate drivers required to fast charge high
power MOSFET gate capacitances. Good supply bypass-
ing is required consisting of a 0.1
μ
F ceramic capacitor in
parallel with a low ESR electrolytic capacitor (56
μ
F or
higher) in close proximity to IC GND.
PWM SECTION
SS2 (Pin 13):
PWM Soft Start. The comparator PWMOK
monitors the OVP pin and releases the SS2 after the PFC
output gets close to the final voltage.
V
C
(Pin 18):
PWM voltage mode control voltage. Normally
connects to the optocoupler amplifier output. A pull-up
current of 50
μ
A flows out of the pin.
I
LIM
(Pin 19):
PWM current sense input with limit set to
1.1V.
GTDR2 (Pin 20):
The PWM MOSFET gate driver is a 1.5A
fast totem pole output. It is clamped at 15V. Capacitive
loads like the MOSFET gates may cause overshoot. A gate
series resistor of at least 5
will prevent the overshoot.
APPLICATIO
S I
FOR
ATIO
U
Voltage Error Amplifier (PFC Section)
The voltage error amplifier has a 100dB DC gain and 3MHz
unity-gain frequency. The output is internally clamped at
13.3V with V
CC
= 18V. Maximum error amp output voltage
decreases to V
CC
– 1.5V for V
CC
less than 12V. The
noninverting input is tied to the 7.5V
REF
through a diode
and can be pulled down with the SS1 pin. Referring to
Figure 1, V
OUT
= V
REF
[(R1 + R2)/R2]. With R1 = 1M and
R2 = 20k, V
OUT
= 382V. R1 through R4, C1 and C2 form the
compensation for the voltage loop. Gain of the voltage
error amp with the values shown is given by:
W
U
U
VA
OUT
V
OUT
= –
1 + j
(j)(f)(6.6)
f
1
f
11
1 + j
)
)
The small-signal gain for the remaining portion of the
voltage loop for frequencies below the current loop band-
width is (see Figure 2):
V
OUT
VA
OUT
V
IN
(5
π)(
j)(f)(C
OUT
)(V
OUT
)
(R
REF
)(P
IN
)
R
S
(R
IAC
+ 25k)
=
C1
0.47
μ
F
7.5V
REF
1.05V
REF
OVERVOLTAGE
COMPARATOR
LT1508
R3
20k
R4
330k
C2
0.047
μ
F
REGULATOR OUTPUT
V
OUT
= 382V
1508 F01
V
SENSE
OVP
VA
OUT
ERROR AMP
R1
1M
R2
20k
–
+
–
+
Figure 1
(For application help with the PFC portion of this chip, see the LT1248 data sheet)
PI
FU
CTIO
N
S
U
U
With V
IN
= 120VAC, P
IN
= 150W, R
S
= 0.15
, R
REF
= 4k,
R
IAC
= 1M, V
OUT
= 382V and C
OUT
= 470
μ
F, V
OUT
/VA
OUT
=
85/(j)(f). At very low frequencies, the loop has a –40dB/
decade slope. Additional zero-pole compensation is added
at 1Hz and 11Hz. The resulting loop gain and phase margin
is shown in Figure 3. The unity-gain bandwidth is low
compared to 120Hz, which results in low distortion and a
high power factor.
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